A novel FPGA architectural implementation of pipelined thinning algorithm

Pei Yung Hsiao; Chun Ho Hua; Chien Chen Lin

A novel FPGA architectural implementation of pipelined thinning algorithm

Pei Yung Hsiao^*, Chun Ho Hua, Chien Chen Lin

^*Corresponding author for this work

Department of Electronic Engineering

Research output: Contribution to journal › Conference article › peer-review

8 Scopus citations

Abstract

Thinning is a very important operation in the image preprocessing stage of pattern recognition. This investigation presents an improved thinning algorithm and its FPGA architectural implementation. The improved algorithm based on parallel pipelined design is adapted and formulated such that it is suitable to computing architecture implementation. The FPGA-based architecture extends the applicability of this algorithm in the area of real time image processing. Using the proposed Modification Unit Array, this work performs thinning operation within 0.07 sec at 40MHz for a 512 × 512 picture.

Original language	English
Pages (from-to)	II593-II596
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2
State	Published - 2004
Event	2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada Duration: 23 05 2004 → 26 05 2004

Cite this

@article{6753997a56004796a06cfe815409521b,

title = "A novel FPGA architectural implementation of pipelined thinning algorithm",

abstract = "Thinning is a very important operation in the image preprocessing stage of pattern recognition. This investigation presents an improved thinning algorithm and its FPGA architectural implementation. The improved algorithm based on parallel pipelined design is adapted and formulated such that it is suitable to computing architecture implementation. The FPGA-based architecture extends the applicability of this algorithm in the area of real time image processing. Using the proposed Modification Unit Array, this work performs thinning operation within 0.07 sec at 40MHz for a 512 × 512 picture.",

author = "Hsiao, \{Pei Yung\} and Hua, \{Chun Ho\} and Lin, \{Chien Chen\}",

year = "2004",

language = "英语",

volume = "2",

pages = "II593--II596",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2004 IEEE International Symposium on Cirquits and Systems - Proceedings ; Conference date: 23-05-2004 Through 26-05-2004",

}

TY - JOUR

T1 - A novel FPGA architectural implementation of pipelined thinning algorithm

AU - Hsiao, Pei Yung

AU - Hua, Chun Ho

AU - Lin, Chien Chen

PY - 2004

Y1 - 2004

N2 - Thinning is a very important operation in the image preprocessing stage of pattern recognition. This investigation presents an improved thinning algorithm and its FPGA architectural implementation. The improved algorithm based on parallel pipelined design is adapted and formulated such that it is suitable to computing architecture implementation. The FPGA-based architecture extends the applicability of this algorithm in the area of real time image processing. Using the proposed Modification Unit Array, this work performs thinning operation within 0.07 sec at 40MHz for a 512 × 512 picture.

AB - Thinning is a very important operation in the image preprocessing stage of pattern recognition. This investigation presents an improved thinning algorithm and its FPGA architectural implementation. The improved algorithm based on parallel pipelined design is adapted and formulated such that it is suitable to computing architecture implementation. The FPGA-based architecture extends the applicability of this algorithm in the area of real time image processing. Using the proposed Modification Unit Array, this work performs thinning operation within 0.07 sec at 40MHz for a 512 × 512 picture.

UR - https://www.scopus.com/pages/publications/4344637823

M3 - 会议文章

AN - SCOPUS:4344637823

SN - 0271-4310

VL - 2

SP - II593-II596

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - 2004 IEEE International Symposium on Cirquits and Systems - Proceedings

Y2 - 23 May 2004 through 26 May 2004

ER -

A novel FPGA architectural implementation of pipelined thinning algorithm

Abstract

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