A Novel In-Loop Filtered Dual Synchronous Reference Frame Phase Locked Loop under Practical Grid Conditions

Phase Locked Loops(PLL) devices are probably the most widely used devices for the estimation of grid parameters voltage, frequency and phase angles. Accurate and prompt estimation of these parameters enhances the speed and ensures the reliability of grid monitoring, protection and control systems. Over the years, there have been many research approaches to design more advanced and sophisticated PLLs to cope up with latest technological requirements of the power grid. Of these various designs, synchronous reference frame PLL had gained more attention owing to their dq frame operation which makes it easier in controller design aspects. In-loop filtered SRFPLLs proposed in literature finely addressed the issue of grid harmonics. This paper proposes a novel In-loop filtered Dual synchronous Reference Frame (DSRF) PLL to enhance the speed of conventional in-loop filtered SRF-PLLs. To assess its performance, three kinds of in-loop filtered SRF-PLLs proposed earlier in literature were taken and compared with the respective in-loop filtered DSRF-PLLs. Experimental results demonstrate the superior performance of DSRF-PLLs compared to conventional SRF-PLLs. It was also observed that using Multiple Delayed Signal Cancellation (MDSC) filter is more advantageous than Cascaded Delayed Signal Cancellation (CDSC) filter and Moving Average Filter (MAF).