A novel memoryless AES cipher architecture for networking applications

Yeong Kang Lai; Li Chung Chang; Lien Fei Chen; Chi Chung Chou; Chun Wei Chiu

A novel memoryless AES cipher architecture for networking applications

Yeong Kang Lai^*
, Li Chung Chang
, Lien Fei Chen
, Chi Chung Chou
, Chun Wei Chiu

^*Corresponding author for this work

National Chung Hsing University

Research output: Contribution to journal › Conference article › peer-review

9 Scopus citations

Abstract

In this paper, we present a novel fast S-box algorithm without lookup table method, and novel fast optional hardware architecture for MixColumn and Inverse MixColumn module with only 5 XOR gate delay. We use on-the-fly key schedule architecture for both encryption and decryption. Furthermore, we implement a memoryless AES cipher with proposed S-box architecture and fast MixColumn and Inverse MixColumn module by adopting pipeline method to obtain high throughput as 1.454Gbits/sec under 125Mhz using 0.25 m CMOS technology and the hardware cost is about 80K gate counts. According to our knowledge, our hardware architecture is the first memoryless AES cipher including encryption and decryption function.

Original language	English
Pages (from-to)	IV-333-IV-336
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	4
State	Published - 2004
Externally published	Yes
Event	2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada Duration: 23 05 2004 → 26 05 2004

Cite this

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title = "A novel memoryless AES cipher architecture for networking applications",

abstract = "In this paper, we present a novel fast S-box algorithm without lookup table method, and novel fast optional hardware architecture for MixColumn and Inverse MixColumn module with only 5 XOR gate delay. We use on-the-fly key schedule architecture for both encryption and decryption. Furthermore, we implement a memoryless AES cipher with proposed S-box architecture and fast MixColumn and Inverse MixColumn module by adopting pipeline method to obtain high throughput as 1.454Gbits/sec under 125Mhz using 0.25 m CMOS technology and the hardware cost is about 80K gate counts. According to our knowledge, our hardware architecture is the first memoryless AES cipher including encryption and decryption function.",

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year = "2004",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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note = "2004 IEEE International Symposium on Cirquits and Systems - Proceedings ; Conference date: 23-05-2004 Through 26-05-2004",

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AU - Lai, Yeong Kang

AU - Chang, Li Chung

AU - Chen, Lien Fei

AU - Chou, Chi Chung

AU - Chiu, Chun Wei

PY - 2004

Y1 - 2004

N2 - In this paper, we present a novel fast S-box algorithm without lookup table method, and novel fast optional hardware architecture for MixColumn and Inverse MixColumn module with only 5 XOR gate delay. We use on-the-fly key schedule architecture for both encryption and decryption. Furthermore, we implement a memoryless AES cipher with proposed S-box architecture and fast MixColumn and Inverse MixColumn module by adopting pipeline method to obtain high throughput as 1.454Gbits/sec under 125Mhz using 0.25 m CMOS technology and the hardware cost is about 80K gate counts. According to our knowledge, our hardware architecture is the first memoryless AES cipher including encryption and decryption function.

AB - In this paper, we present a novel fast S-box algorithm without lookup table method, and novel fast optional hardware architecture for MixColumn and Inverse MixColumn module with only 5 XOR gate delay. We use on-the-fly key schedule architecture for both encryption and decryption. Furthermore, we implement a memoryless AES cipher with proposed S-box architecture and fast MixColumn and Inverse MixColumn module by adopting pipeline method to obtain high throughput as 1.454Gbits/sec under 125Mhz using 0.25 m CMOS technology and the hardware cost is about 80K gate counts. According to our knowledge, our hardware architecture is the first memoryless AES cipher including encryption and decryption function.

UR - https://www.scopus.com/pages/publications/4344659905

M3 - 会议文章

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SN - 0271-4310

VL - 4

SP - IV-333-IV-336

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - 2004 IEEE International Symposium on Cirquits and Systems - Proceedings

Y2 - 23 May 2004 through 26 May 2004

ER -

A novel memoryless AES cipher architecture for networking applications

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