A novel vertical bottom-gate polysilicon thin film transistor with self-aligned offset

Chao Sung Lai; Chung Len Lee; Tan Fu Lei; Horng Nan Chern

doi:10.1109/55.491828

A novel vertical bottom-gate polysilicon thin film transistor with self-aligned offset

Chao Sung Lai^*, Chung Len Lee, Tan Fu Lei, Horng Nan Chern

^*Corresponding author for this work

National Yang Ming Chiao Tung University

Research output: Contribution to journal › Journal Article › peer-review

13 Scopus citations

Abstract

A novel device structure for the vertical bottom polysilicon gate thin film transistor (TFT) with a self-align offset drain is proposed and demonstrated. The new VTFT allows a deep-submicron channel length, which is determined by the thickness of the active polysilicon film, not by the lithographic system resolution. The self-alignment offset drain reduces the leakage current, as a result, it exhibits good device performance.

Original language	English
Pages (from-to)	199-201
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	17
Issue number	5
DOIs	https://doi.org/10.1109/55.491828
State	Published - 05 1996
Externally published	Yes

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title = "A novel vertical bottom-gate polysilicon thin film transistor with self-aligned offset",

abstract = "A novel device structure for the vertical bottom polysilicon gate thin film transistor (TFT) with a self-align offset drain is proposed and demonstrated. The new VTFT allows a deep-submicron channel length, which is determined by the thickness of the active polysilicon film, not by the lithographic system resolution. The self-alignment offset drain reduces the leakage current, as a result, it exhibits good device performance.",

author = "Lai, {Chao Sung} and Lee, {Chung Len} and Lei, {Tan Fu} and Chern, {Horng Nan}",

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AU - Lee, Chung Len

AU - Lei, Tan Fu

AU - Chern, Horng Nan

PY - 1996/5

Y1 - 1996/5

N2 - A novel device structure for the vertical bottom polysilicon gate thin film transistor (TFT) with a self-align offset drain is proposed and demonstrated. The new VTFT allows a deep-submicron channel length, which is determined by the thickness of the active polysilicon film, not by the lithographic system resolution. The self-alignment offset drain reduces the leakage current, as a result, it exhibits good device performance.

AB - A novel device structure for the vertical bottom polysilicon gate thin film transistor (TFT) with a self-align offset drain is proposed and demonstrated. The new VTFT allows a deep-submicron channel length, which is determined by the thickness of the active polysilicon film, not by the lithographic system resolution. The self-alignment offset drain reduces the leakage current, as a result, it exhibits good device performance.

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A novel vertical bottom-gate polysilicon thin film transistor with self-aligned offset

Abstract

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