A novel video signal processor with programmable data arrangement and efficient memory configuration

Yeong Kang Lai; Liang Gee Chen; Hsu Tung Chen; Mei Juan Chen; Yung Pin Lee; Po Cheng Wu

doi:10.1109/30.536152

A novel video signal processor with programmable data arrangement and efficient memory configuration

Yeong Kang Lai, Liang Gee Chen, Hsu Tung Chen, Mei Juan Chen, Yung Pin Lee, Po Cheng Wu

National Taiwan University

Research output: Contribution to journal › Journal Article › peer-review

4 Scopus citations

Abstract

This paper describes a novel Video Signal Processor (VSP) with the fully pipelined parallel architecture for video browsing, coding, and image processing for multimedia systems. The efficiency of the architecture developed is increased by use of programmable data arrangement and intelligent memory configuration. Techniques for reducing interconnections and external memory accesses are also presented. Due to the properties of low cost, high speed, and low memory bandwidth requirements, the VSP provides efficient solutions for video signal processing applications.

Original language	English
Pages (from-to)	526-534
Number of pages	9
Journal	IEEE Transactions on Consumer Electronics
Volume	42
Issue number	3
DOIs	https://doi.org/10.1109/30.536152
State	Published - 1996
Externally published	Yes

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10.1109/30.536152

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abstract = "This paper describes a novel Video Signal Processor (VSP) with the fully pipelined parallel architecture for video browsing, coding, and image processing for multimedia systems. The efficiency of the architecture developed is increased by use of programmable data arrangement and intelligent memory configuration. Techniques for reducing interconnections and external memory accesses are also presented. Due to the properties of low cost, high speed, and low memory bandwidth requirements, the VSP provides efficient solutions for video signal processing applications.",

author = "Lai, {Yeong Kang} and Chen, {Liang Gee} and Chen, {Hsu Tung} and Chen, {Mei Juan} and Lee, {Yung Pin} and Wu, {Po Cheng}",

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AU - Wu, Po Cheng

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AB - This paper describes a novel Video Signal Processor (VSP) with the fully pipelined parallel architecture for video browsing, coding, and image processing for multimedia systems. The efficiency of the architecture developed is increased by use of programmable data arrangement and intelligent memory configuration. Techniques for reducing interconnections and external memory accesses are also presented. Due to the properties of low cost, high speed, and low memory bandwidth requirements, the VSP provides efficient solutions for video signal processing applications.

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A novel video signal processor with programmable data arrangement and efficient memory configuration

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