A parallel decoder design for low latency turbo decoding

Ya Cheng Lu*, Erl Huei Lu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

To reduce the iterative decoding time in turbo coding, a new parallel decoding algorithm for turbo decoders is proposed. Different than the previous approaches of using multiple SISO decoders to process sub-block MAP decoding in parallel, the new parallel turbo decoder immediately passes the extrinsic information of each message bit which is generated by one SISO decoder to the other SISO decoders bit by bit. Thus, the component decoders corresponding to different received sequence perform in parallel and the interleaver delay is eliminated. Simulation results show that with this parallel scheme, decoding time is halved while the performance in terms of BER is comparable, and in some cases superior, to the general turbo decoder.

Original languageEnglish
Title of host publicationSecond International Conference on Innovative Computing, Information and Control, ICICIC 2007
PublisherIEEE Computer Society
ISBN (Print)0769528821, 9780769528823
DOIs
StatePublished - 2007
Event2nd International Conference on Innovative Computing, Information and Control, ICICIC 2007 - Kumamoto, Japan
Duration: 05 09 200707 09 2007

Publication series

NameSecond International Conference on Innovative Computing, Information and Control, ICICIC 2007

Conference

Conference2nd International Conference on Innovative Computing, Information and Control, ICICIC 2007
Country/TerritoryJapan
CityKumamoto
Period05/09/0707/09/07

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