A parameterized-dispatching rule for a Logic IC sort in a wafer fabrication

In this paper, a parameterized dispatching rule (PDR) using the response surface method is presented for a Logic IC sort in a wafer fabrication. A broad product mix, variable lot sizes and yields, long and variable set-up times, and limited test equipment capacity can characterize the operations in this wafer probe centre. The objective of this study is to simultaneously optimize the desirability function that is the combination of multiple attributes of the products such as the hot lot or normal lot, critical ratio with good on-time delivery performance, processing time, set-up time, waiting time, and machine flexibility. This is accomplished by combining the multiple attributes together using a linear combination with relative weights. Also, multiple performance measures are considered in this study. Discrete event simulation models based on eM-Plant are developed to implement the proposed rule. The comparison is also made with other rules such as shortest set-up time (SST), shortest processing time (SPT), shortest set-up and processing time (SSPT), smallest critical ratio (SCR), first in first out (FIFO) and least machine flexibility (LMF). Here, two combined performance values are used as the performance measure that both are combined with the multiple performance measures to a single value using the desirability function. The simulation results show that the four proposed PDRs outperform other rules in many different operational conditions.