A phase-locked loop with background self-calibration for phase error reduction

The proposed phase-locked loop system constructs with the current-mismatch adjusting circuit reduces the static phase error. The proposed current-mismatch adjusting circuit uses a time amplifier circuit to enlarge the phase error between the Up and Dn pulses. The digital code from the current mismatch adjusting circuit calibrates the charge current in the charge pump. The circuit is fabricated in a 0.35 μm CMOS process with 3.3 V supply voltage. The measured static phase error without and with current-mismatch adjusting circuit is 65.41 and 3.44ps, respectively.