A Probabilistic estimation bias circuit for fixed-width Booth multiplier and its DCT applications

In this brief, a probabilistic estimation bias (PEB) circuit for a fixed-width two's-complement Booth multiplier is proposed. The proposed PEB circuit is derived from theoretical computation, instead of exhaustive simulations and heuristic compensation strategies that tend to introduce curve-fitting errors and exponential-grown simulation time. Consequently, the proposed PEB circuit provides a smaller area and a lower truncation error compared with existing works. Implemented in an 8 × 8 2-D discrete cosine transform (DCT) core, the DCT core using the proposed PEB Booth multiplier mproves the peak signal-to-noise ratio by 17 dB with only a 2% area penalty compared with the direct-truncated method.