A pulse-width control loop for power electronics applications

More and more systems use double-sampling or double data rate techniques to ensure electronic products to have high performance and low power dissipation simultaneously. In these systems, a symmetrical clock signal with 50% duty cycle is very important. However, the process, voltage, and temperature variations may change the duty cycle of the used clock. In order to suppress the variations effects, a pulse-width control loop is generally required for these applications. Therefore, in this paper we propose a new control loop which can operate well up to several hundred MHz based on 0.18um CMOS process. Due to the voltage limited charge pump, the lock-time is greatly reduced as compared to other existing prior art circuits. Besides, the acceptable duty range of the input signal varies from 20% to 80%. The validity of the proposed circuit has been verified by test chip results. Therefore, the presented pulse-width control loop can be used for power drives and power electronics applications.