A real-time FPGA based human detector

Pei Yung Hsiao, Shih Yu Lin, Chuen Yau Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

14 Scopus citations

Abstract

An ARM-platform and FPGA-based accelerator rather than PC-based system is utilized in this study for completing a real-time FPGA-based human detector. The system presents the advantages of small size, low cost, high computing speed, and being portable and could be built in small cameras for surveillance applications. When background segmentation is introduced, the computing efficiency could reach about 15 fps. Moreover, this study has proven that the reduction on the total detection rate is less than 0.3% while changing HOG algorithm into the presented FPGA hardware implementation.

Original languageEnglish
Title of host publicationProceedings - 2016 IEEE International Symposium on Computer, Consumer and Control, IS3C 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1014-1017
Number of pages4
ISBN (Electronic)9781509030712
DOIs
StatePublished - 16 08 2016
Externally publishedYes
Event2016 IEEE International Symposium on Computer, Consumer and Control, IS3C 2016 - Xi'an, China
Duration: 04 07 201606 07 2016

Publication series

NameProceedings - 2016 IEEE International Symposium on Computer, Consumer and Control, IS3C 2016

Conference

Conference2016 IEEE International Symposium on Computer, Consumer and Control, IS3C 2016
Country/TerritoryChina
CityXi'an
Period04/07/1606/07/16

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

Keywords

  • FPGA Accelerator
  • HOG
  • Human Detection
  • Machine Learning
  • Real-Time Embedded System

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