A reconfigurable IDCT architecture for universal video decoders

Nowadays, the reconfigurable architecture has become more and more popular. It not only decreases the time of research and development but also saves fabrication cost. Moreover, the proposed reconfigurable inverse discrete cosine transform (IDCT) architecture can support various video standards such as VC-1, MPEG-1/2/4 and H.264 AVC. It can sustain four transform types, 8 × 8, 8 × 4, 4 × 8, and 4 × 4 transform. The advantages of the proposed architecture are that this architecture does not require multipliers and ROM. It only needs adders and shifters. In digital circuits, the area of the multipliers and ROM are larger than adders and shifters. In order to reduce power consumption, we implement this reconfigurable architecture by using 90nm process technology to accomplish our chip design. The simulation result shows that the power consumption is only 3.4mW at 100MHz. The processor can perform HDTV 720p and HDTV 1080p in real-time. Briefly, the proposed architecture is regular, low power and reconfigurable. Therefore, it can be applied in universal video decoders.