A scalable DCO design for portable ADPLL designs

Chia Tsun Wu; Wei Wang; I. Chyn Wey; An Yeu Wu

doi:10.1109/ISCAS.2005.1465869

A scalable DCO design for portable ADPLL designs

Chia Tsun Wu^*, Wei Wang, I. Chyn Wey, An Yeu Wu

^*Corresponding author for this work

National Taiwan University

Research output: Contribution to journal › Conference article › peer-review

19 Scopus citations

Abstract

A novel Digital Controlled Oscillator (DCO) design methodology is presented in this paper. The new design methodology includes a scalable DCO architecture and the developed design flow. With precise analysis in early stage, the design effort of DCO can be reduced significantly. The proposed DCO architecture has the characteristics of, high resolution, flexible operating range, and easy design. The design is suitable for high performance clock generator in System on a Chip (SoC) application.

Original language	English
Article number	1465869
Pages (from-to)	5449-5452
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2005.1465869
State	Published - 2005
Externally published	Yes
Event	IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: 23 05 2005 → 26 05 2005

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10.1109/ISCAS.2005.1465869

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title = "A scalable DCO design for portable ADPLL designs",

abstract = "A novel Digital Controlled Oscillator (DCO) design methodology is presented in this paper. The new design methodology includes a scalable DCO architecture and the developed design flow. With precise analysis in early stage, the design effort of DCO can be reduced significantly. The proposed DCO architecture has the characteristics of, high resolution, flexible operating range, and easy design. The design is suitable for high performance clock generator in System on a Chip (SoC) application.",

author = "Wu, \{Chia Tsun\} and Wei Wang and Wey, \{I. Chyn\} and Wu, \{An Yeu\}",

year = "2005",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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AU - Wu, Chia Tsun

AU - Wang, Wei

AU - Wey, I. Chyn

AU - Wu, An Yeu

PY - 2005

Y1 - 2005

N2 - A novel Digital Controlled Oscillator (DCO) design methodology is presented in this paper. The new design methodology includes a scalable DCO architecture and the developed design flow. With precise analysis in early stage, the design effort of DCO can be reduced significantly. The proposed DCO architecture has the characteristics of, high resolution, flexible operating range, and easy design. The design is suitable for high performance clock generator in System on a Chip (SoC) application.

AB - A novel Digital Controlled Oscillator (DCO) design methodology is presented in this paper. The new design methodology includes a scalable DCO architecture and the developed design flow. With precise analysis in early stage, the design effort of DCO can be reduced significantly. The proposed DCO architecture has the characteristics of, high resolution, flexible operating range, and easy design. The design is suitable for high performance clock generator in System on a Chip (SoC) application.

UR - https://www.scopus.com/pages/publications/48049096467

U2 - 10.1109/ISCAS.2005.1465869

DO - 10.1109/ISCAS.2005.1465869

M3 - 会议文章

AN - SCOPUS:48049096467

SN - 0271-4310

SP - 5449

EP - 5452

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

M1 - 1465869

T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005

Y2 - 23 May 2005 through 26 May 2005

ER -

A scalable DCO design for portable ADPLL designs

Abstract

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