Abstract
Digital annealing is a technology that has emerged to address the difficulty of implementing quantum annealing. Traditional CMOS is used to approximate quantum annealing operations, which don't need to operate in extreme environments. The functionality of this chip has been simplified for computations of simulated annealing algorithms, Efficiently update spins by reducing computational overhead from O(N2) to O(N) multiplications. and simplifying the traditional Metropolis's Law for ease of hardware implementation. The chip is fabricated using the TSMC TN90GUTM process, with a designed operating frequency of 60MHz, capable of reaching a maximum of 141MHz, and the chip area is 0.9mm ×0.9mm.
| Original language | English |
|---|---|
| Title of host publication | GCCE 2024 - 2024 IEEE 13th Global Conference on Consumer Electronics |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 1262-1264 |
| Number of pages | 3 |
| ISBN (Electronic) | 9798350355079 |
| DOIs | |
| State | Published - 2024 |
| Event | 13th IEEE Global Conference on Consumer Electronic, GCCE 2024 - Kitakyushu, Japan Duration: 29 10 2024 → 01 11 2024 |
Publication series
| Name | GCCE 2024 - 2024 IEEE 13th Global Conference on Consumer Electronics |
|---|
Conference
| Conference | 13th IEEE Global Conference on Consumer Electronic, GCCE 2024 |
|---|---|
| Country/Territory | Japan |
| City | Kitakyushu |
| Period | 29/10/24 → 01/11/24 |
Bibliographical note
Publisher Copyright:© 2024 IEEE.
Keywords
- Digital annealing
- Quantum annealing
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