A Simulation-Based Temporal Assertion Checker for PSL

Kai Hui Chang; Wei Ting Tu; Yi Jong Yeh; Sy Yen Kuo

doi:10.1109/MWSCAS.2003.1562587

A Simulation-Based Temporal Assertion Checker for PSL

Kai Hui Chang, Wei Ting Tu, Yi Jong Yeh, Sy Yen Kuo

National Taiwan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

A simulation-based temporal assertion verification engine for PSL (Property Specification Language), called Tempral Wizard, is proposed in this paper. It is very efficient because its time and space complexity are both O(n). A new concept, tag, is introduced in Tempral Wizard and it handles the forall operator elegantly.

Original language	English
Title of host publication	Midwest Symposium on Circuits and Systems
Editors	Nadder Hamdy
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1528-1531
Number of pages	4
ISBN (Electronic)	0780382943
DOIs	https://doi.org/10.1109/MWSCAS.2003.1562587
State	Published - 2003
Externally published	Yes
Event	46th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2003 - Cairo, Egypt Duration: 27 12 2003 → 30 12 2003

Publication series

Name	Midwest Symposium on Circuits and Systems
Volume	3
ISSN (Print)	1548-3746

Conference

Conference	46th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2003
Country/Territory	Egypt
City	Cairo
Period	27/12/03 → 30/12/03

Bibliographical note

Publisher Copyright:
© 2004 IEEE.

Access to Document

10.1109/MWSCAS.2003.1562587

Cite this

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title = "A Simulation-Based Temporal Assertion Checker for PSL",

abstract = "A simulation-based temporal assertion verification engine for PSL (Property Specification Language), called Tempral Wizard, is proposed in this paper. It is very efficient because its time and space complexity are both O(n). A new concept, tag, is introduced in Tempral Wizard and it handles the forall operator elegantly.",

author = "Chang, {Kai Hui} and Tu, {Wei Ting} and Yeh, {Yi Jong} and Kuo, {Sy Yen}",

note = "Publisher Copyright: {\textcopyright} 2004 IEEE.; 46th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2003 ; Conference date: 27-12-2003 Through 30-12-2003",

year = "2003",

doi = "10.1109/MWSCAS.2003.1562587",

language = "英语",

series = "Midwest Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Chang, KH, Tu, WT, Yeh, YJ & Kuo, SY 2003, A Simulation-Based Temporal Assertion Checker for PSL. in N Hamdy (ed.), Midwest Symposium on Circuits and Systems. Midwest Symposium on Circuits and Systems, vol. 3, Institute of Electrical and Electronics Engineers Inc., pp. 1528-1531, 46th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2003, Cairo, Egypt, 27/12/03. https://doi.org/10.1109/MWSCAS.2003.1562587

A Simulation-Based Temporal Assertion Checker for PSL. / Chang, Kai Hui; Tu, Wei Ting; Yeh, Yi Jong et al.
Midwest Symposium on Circuits and Systems. ed. / Nadder Hamdy. Institute of Electrical and Electronics Engineers Inc., 2003. p. 1528-1531 (Midwest Symposium on Circuits and Systems; Vol. 3).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - A simulation-based temporal assertion verification engine for PSL (Property Specification Language), called Tempral Wizard, is proposed in this paper. It is very efficient because its time and space complexity are both O(n). A new concept, tag, is introduced in Tempral Wizard and it handles the forall operator elegantly.

AB - A simulation-based temporal assertion verification engine for PSL (Property Specification Language), called Tempral Wizard, is proposed in this paper. It is very efficient because its time and space complexity are both O(n). A new concept, tag, is introduced in Tempral Wizard and it handles the forall operator elegantly.

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A Simulation-Based Temporal Assertion Checker for PSL

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