A study of overlaying dielectric layer and its local geometry effects on TSV-induced KOZ in 3-D IC

The aim of this paper is to investigate the effects of overlaying dielectric layer and its local geometry on keep-out zone (KOZ) induced from through-silicon via (TSV) in 3-D integrated circuit applications. Prior to the study, the saturated current changes (or corresponding carrier mobility changes) of both nMOS and pMOS transistors from the finite element simulations are validated with experimental data. After the model verification, six cases with various local dielectric structures are proposed to minimize KOZ. The results show that the case with an embedded SiO₂ on the top of Cu TSV has the least effect on saturated current change (or the minimum KOZ) among those cases. Furthermore, the various embedded-SiO₂ depths on the top of Cu TSV are further investigated. It is found that saturated current change of pMOS placed in both horizontal and vertical directions on Si substrate can be minimized using a 6-μm-deep embedded SiO₂. Besides those results, the effects of other parameters such as the thickness of overlaying dielectric layer, shallow trench isolation, and silicon crystal orientations of [110] and [100] are also presented and discussed in this paper.