A Temporal Assertion Extension to Verilog

Kai Hui Chang; Wei Ting Tu; Yi Jong Yeh; Sy Yen Kuo

doi:10.1007/978-3-540-30476-0_45

A Temporal Assertion Extension to Verilog

Kai Hui Chang^*
, Wei Ting Tu
, Yi Jong Yeh
, Sy Yen Kuo

^*Corresponding author for this work

National Taiwan University

Research output: Chapter in Book/Report/Conference proceeding › Chapter › peer-review

1 Scopus citations

Abstract

Many circuit designs need to follow some temporal rules. However, it is hard to express and verify them in the past. Therefore, a temporal assertion extension to Verilog, called Temporal Wizard, is proposed in this paper. It provides several Verilog system tasks for the users to write assertions in testbench directly. Two new concepts, tag and thread, are also introduced so that data can be associated with temporal assertions and provide more functionalities than previous temporal assertion checkers.

Original language	English
Title of host publication	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Editors	Farn Wang
Publisher	Springer Verlag
Pages	499-504
Number of pages	6
ISBN (Print)	9783540236108
DOIs	https://doi.org/10.1007/978-3-540-30476-0_45
State	Published - 2004
Externally published	Yes

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	3299
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Keywords

PSL
Temporal assertion
Verification

Access to Document

10.1007/978-3-540-30476-0_45

Cite this

Chang, K. H., Tu, W. T., Yeh, Y. J., & Kuo, S. Y. (2004). A Temporal Assertion Extension to Verilog. In F. Wang (Ed.), Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (pp. 499-504). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 3299). Springer Verlag. https://doi.org/10.1007/978-3-540-30476-0_45

Chang, Kai Hui ; Tu, Wei Ting ; Yeh, Yi Jong et al. / A Temporal Assertion Extension to Verilog. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). editor / Farn Wang. Springer Verlag, 2004. pp. 499-504 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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abstract = "Many circuit designs need to follow some temporal rules. However, it is hard to express and verify them in the past. Therefore, a temporal assertion extension to Verilog, called Temporal Wizard, is proposed in this paper. It provides several Verilog system tasks for the users to write assertions in testbench directly. Two new concepts, tag and thread, are also introduced so that data can be associated with temporal assertions and provide more functionalities than previous temporal assertion checkers.",

keywords = "PSL, Temporal assertion, Verification",

author = "Chang, \{Kai Hui\} and Tu, \{Wei Ting\} and Yeh, \{Yi Jong\} and Kuo, \{Sy Yen\}",

year = "2004",

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series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

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Chang, KH, Tu, WT, Yeh, YJ & Kuo, SY 2004, A Temporal Assertion Extension to Verilog. in F Wang (ed.), Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 3299, Springer Verlag, pp. 499-504. https://doi.org/10.1007/978-3-540-30476-0_45

A Temporal Assertion Extension to Verilog. / Chang, Kai Hui; Tu, Wei Ting; Yeh, Yi Jong et al.
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). ed. / Farn Wang. Springer Verlag, 2004. p. 499-504 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 3299).

Research output: Chapter in Book/Report/Conference proceeding › Chapter › peer-review

TY - CHAP

T1 - A Temporal Assertion Extension to Verilog

AU - Chang, Kai Hui

AU - Tu, Wei Ting

AU - Yeh, Yi Jong

AU - Kuo, Sy Yen

PY - 2004

Y1 - 2004

N2 - Many circuit designs need to follow some temporal rules. However, it is hard to express and verify them in the past. Therefore, a temporal assertion extension to Verilog, called Temporal Wizard, is proposed in this paper. It provides several Verilog system tasks for the users to write assertions in testbench directly. Two new concepts, tag and thread, are also introduced so that data can be associated with temporal assertions and provide more functionalities than previous temporal assertion checkers.

AB - Many circuit designs need to follow some temporal rules. However, it is hard to express and verify them in the past. Therefore, a temporal assertion extension to Verilog, called Temporal Wizard, is proposed in this paper. It provides several Verilog system tasks for the users to write assertions in testbench directly. Two new concepts, tag and thread, are also introduced so that data can be associated with temporal assertions and provide more functionalities than previous temporal assertion checkers.

KW - PSL

KW - Temporal assertion

KW - Verification

UR - https://www.scopus.com/pages/publications/26844565409

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DO - 10.1007/978-3-540-30476-0_45

M3 - 章节

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SN - 9783540236108

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 499

EP - 504

BT - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

A2 - Wang, Farn

PB - Springer Verlag

ER -

Chang KH, Tu WT, Yeh YJ, Kuo SY. A Temporal Assertion Extension to Verilog. In Wang F, editor, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag. 2004. p. 499-504. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-540-30476-0_45

A Temporal Assertion Extension to Verilog

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