A unified submicrometer MOS transistor charge/capacitance model for mixed-signal IC's

Steve H. Jen; Bing J. Sheu; Yoondong Park

doi:10.1109/4.736662

A unified submicrometer MOS transistor charge/capacitance model for mixed-signal IC's

Steve H. Jen^*, Bing J. Sheu, Yoondong Park

^*Corresponding author for this work

University of Southern California

Research output: Contribution to journal › Journal Article › peer-review

3 Scopus citations

Abstract

A unified modeling approach for the submicrometer MOS transistor charge/capacitance characteristics in all operation regions is presented. Development of this MOS charge model is based on the charge-density approximation to reduce the complexity of the analytical expression. To model the charge density more accurately, the conductance-degradation coefficient is determined by the derivative of drain-to-source saturation voltage with respect to gate-to-channel potential. The unified charge densities in gate, channel, and bulk regions are obtained with the assistance of the sigmoid, hyperbola, and exponential interpolation techniques. Good agreement between the measurement data and simulation results is obtained.

Original language	English
Pages (from-to)	103-106
Number of pages	4
Journal	IEEE Journal of Solid-State Circuits
Volume	34
Issue number	1
DOIs	https://doi.org/10.1109/4.736662
State	Published - 01 1999
Externally published	Yes

Keywords

Analog circuit
Capacitance
Charge
Circuit model
Integrated circuit
Silicon technology

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10.1109/4.736662

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title = "A unified submicrometer MOS transistor charge/capacitance model for mixed-signal IC's",

abstract = "A unified modeling approach for the submicrometer MOS transistor charge/capacitance characteristics in all operation regions is presented. Development of this MOS charge model is based on the charge-density approximation to reduce the complexity of the analytical expression. To model the charge density more accurately, the conductance-degradation coefficient is determined by the derivative of drain-to-source saturation voltage with respect to gate-to-channel potential. The unified charge densities in gate, channel, and bulk regions are obtained with the assistance of the sigmoid, hyperbola, and exponential interpolation techniques. Good agreement between the measurement data and simulation results is obtained.",

keywords = "Analog circuit, Capacitance, Charge, Circuit model, Integrated circuit, Silicon technology",

author = "Jen, {Steve H.} and Sheu, {Bing J.} and Yoondong Park",

year = "1999",

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AU - Sheu, Bing J.

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N2 - A unified modeling approach for the submicrometer MOS transistor charge/capacitance characteristics in all operation regions is presented. Development of this MOS charge model is based on the charge-density approximation to reduce the complexity of the analytical expression. To model the charge density more accurately, the conductance-degradation coefficient is determined by the derivative of drain-to-source saturation voltage with respect to gate-to-channel potential. The unified charge densities in gate, channel, and bulk regions are obtained with the assistance of the sigmoid, hyperbola, and exponential interpolation techniques. Good agreement between the measurement data and simulation results is obtained.

AB - A unified modeling approach for the submicrometer MOS transistor charge/capacitance characteristics in all operation regions is presented. Development of this MOS charge model is based on the charge-density approximation to reduce the complexity of the analytical expression. To model the charge density more accurately, the conductance-degradation coefficient is determined by the derivative of drain-to-source saturation voltage with respect to gate-to-channel potential. The unified charge densities in gate, channel, and bulk regions are obtained with the assistance of the sigmoid, hyperbola, and exponential interpolation techniques. Good agreement between the measurement data and simulation results is obtained.

KW - Analog circuit

KW - Capacitance

KW - Charge

KW - Circuit model

KW - Integrated circuit

KW - Silicon technology

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JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

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ER -

A unified submicrometer MOS transistor charge/capacitance model for mixed-signal IC's

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Keywords

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