A wide-range all-digital duty cycle corrector with a period monitor

Shao Ku Kao; Shen Iuan Liu

doi:10.1109/EDSSC.2007.4450134

A wide-range all-digital duty cycle corrector with a period monitor

Shao Ku Kao^*, Shen Iuan Liu

^*Corresponding author for this work

National Taiwan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

13 Scopus citations

Abstract

A wide-range all-digital duty cycle corrector (DCC) with a period monitor is presented. It corrects the duty cycle within four cycles. It generates the output clock of 50% duty cycle when the input duty cycle is within 10% - 90%. After this DCC locked, a closed-loop monitor continuously tracks the period of input clock to keep 50% duty-cycle in every eight cycles. The proposed circuit has been fabricated in a 0.18um CMOS technology. The measured duty cycle error is between 1.3% and 1.6% and the measured frequency range is from 1GHz to 1.6GHz.

Original language	English
Title of host publication	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
Pages	349-352
Number of pages	4
DOIs	https://doi.org/10.1109/EDSSC.2007.4450134
State	Published - 2007
Externally published	Yes
Event	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 - Tainan, Taiwan Duration: 20 12 2007 → 22 12 2007

Publication series

Name	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

Conference

Conference	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
Country/Territory	Taiwan
City	Tainan
Period	20/12/07 → 22/12/07

Keywords

All-digital
Duty cycle
Duty cycle corrector

Access to Document

10.1109/EDSSC.2007.4450134

Cite this

@inproceedings{30a587f04bdf46689a01b293099aee34,

title = "A wide-range all-digital duty cycle corrector with a period monitor",

abstract = "A wide-range all-digital duty cycle corrector (DCC) with a period monitor is presented. It corrects the duty cycle within four cycles. It generates the output clock of 50% duty cycle when the input duty cycle is within 10% - 90%. After this DCC locked, a closed-loop monitor continuously tracks the period of input clock to keep 50% duty-cycle in every eight cycles. The proposed circuit has been fabricated in a 0.18um CMOS technology. The measured duty cycle error is between 1.3% and 1.6% and the measured frequency range is from 1GHz to 1.6GHz.",

keywords = "All-digital, Duty cycle, Duty cycle corrector",

author = "Kao, {Shao Ku} and Liu, {Shen Iuan}",

year = "2007",

doi = "10.1109/EDSSC.2007.4450134",

language = "英语",

isbn = "1424406374",

series = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007",

pages = "349--352",

booktitle = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007",

note = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 ; Conference date: 20-12-2007 Through 22-12-2007",

}

Kao, SK & Liu, SI 2007, A wide-range all-digital duty cycle corrector with a period monitor. in IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007., 4450134, IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007, pp. 349-352, IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007, Tainan, Taiwan, 20/12/07. https://doi.org/10.1109/EDSSC.2007.4450134

A wide-range all-digital duty cycle corrector with a period monitor. / Kao, Shao Ku; Liu, Shen Iuan.
IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007. 2007. p. 349-352 4450134 (IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A wide-range all-digital duty cycle corrector with a period monitor

AU - Kao, Shao Ku

AU - Liu, Shen Iuan

PY - 2007

Y1 - 2007

N2 - A wide-range all-digital duty cycle corrector (DCC) with a period monitor is presented. It corrects the duty cycle within four cycles. It generates the output clock of 50% duty cycle when the input duty cycle is within 10% - 90%. After this DCC locked, a closed-loop monitor continuously tracks the period of input clock to keep 50% duty-cycle in every eight cycles. The proposed circuit has been fabricated in a 0.18um CMOS technology. The measured duty cycle error is between 1.3% and 1.6% and the measured frequency range is from 1GHz to 1.6GHz.

AB - A wide-range all-digital duty cycle corrector (DCC) with a period monitor is presented. It corrects the duty cycle within four cycles. It generates the output clock of 50% duty cycle when the input duty cycle is within 10% - 90%. After this DCC locked, a closed-loop monitor continuously tracks the period of input clock to keep 50% duty-cycle in every eight cycles. The proposed circuit has been fabricated in a 0.18um CMOS technology. The measured duty cycle error is between 1.3% and 1.6% and the measured frequency range is from 1GHz to 1.6GHz.

KW - All-digital

KW - Duty cycle

KW - Duty cycle corrector

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DO - 10.1109/EDSSC.2007.4450134

M3 - 会议稿件

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SN - 9781424406371

T3 - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

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BT - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

T2 - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

Y2 - 20 December 2007 through 22 December 2007

ER -

A wide-range all-digital duty cycle corrector with a period monitor

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Conference

Keywords

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