Advanced Integrated-Circuit Reliability Simulation Including Dynamic Stress Effects

Wen Jay Hsu, Bing J. Sheu, Sudhir M. Gowda, Chang Gyu Hwang

Research output: Contribution to journalJournal Article peer-review

18 Scopus citations

Abstract

Advanced design of very large-scale integration (VLSI) computing circuits requires an accurate means of assessing hardware reliability in order to fully utilize the great potential of submicrometer fabrication technologies. A systematic approach to predict semiconductor degradation effects using reliability simulation is described. The dc degradation monitor is first extracted during transient circuit simulation. An ac degradation factor is then used to determine circuit performance degradation. By using these techniques on the design of CMOS components, proper long-term reliability can be achieved for high-speed circuits. Experimental results on digital circuits using an industrial submicrometer technology demonstrate the effectiveness of this approach in reliable VLSI circuit design. Results on two-input nand gates, DRAM precharging circuit, and SRAM control circuits are presented.

Original languageEnglish
Pages (from-to)247-257
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume27
Issue number3
DOIs
StatePublished - 03 1992
Externally publishedYes

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