All-Digital Fast-Locked Synchronous Duty-Cycle Corrector

Shao Ku Kao; Shen Iuan Liu

doi:10.1109/TCSII.2006.885396

All-Digital Fast-Locked Synchronous Duty-Cycle Corrector

Shao Ku Kao
, Shen Iuan Liu

National Taiwan University

Research output: Contribution to journal › Journal Article › peer-review

38 Scopus citations

Abstract

An all-digital fast-locked synchronous duty-cycle corrector is presented. It corrects the duty cycle and synchronizes the input and output clocks in 10 clock cycles. The proposed circuit has been fabricated in a 0.18- μ m CMOS technology. The measured duty-cycle error is between 1.5% and —1.4% for the input duty cycle of 40% ~ 60%. The measured peak-to-peak jitter is 12.9 ps at 1 GHz. The measured operation frequency range is from 0.8 GHz to 1.2 GHz.

Original language	English
Pages (from-to)	1363-1367
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	53
Issue number	12
DOIs	https://doi.org/10.1109/TCSII.2006.885396
State	Published - 12 2006
Externally published	Yes

Keywords

All-digital
duty-cycle corrector (DCC)
fast-locked

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10.1109/TCSII.2006.885396

Cite this

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title = "All-Digital Fast-Locked Synchronous Duty-Cycle Corrector",

abstract = "An all-digital fast-locked synchronous duty-cycle corrector is presented. It corrects the duty cycle and synchronizes the input and output clocks in 10 clock cycles. The proposed circuit has been fabricated in a 0.18- μ m CMOS technology. The measured duty-cycle error is between 1.5\% and —1.4\% for the input duty cycle of 40\% \textasciitilde{} 60\%. The measured peak-to-peak jitter is 12.9 ps at 1 GHz. The measured operation frequency range is from 0.8 GHz to 1.2 GHz.",

keywords = "All-digital, duty-cycle corrector (DCC), fast-locked",

author = "Kao, \{Shao Ku\} and Liu, \{Shen Iuan\}",

year = "2006",

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doi = "10.1109/TCSII.2006.885396",

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volume = "53",

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AU - Liu, Shen Iuan

PY - 2006/12

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N2 - An all-digital fast-locked synchronous duty-cycle corrector is presented. It corrects the duty cycle and synchronizes the input and output clocks in 10 clock cycles. The proposed circuit has been fabricated in a 0.18- μ m CMOS technology. The measured duty-cycle error is between 1.5% and —1.4% for the input duty cycle of 40% ~ 60%. The measured peak-to-peak jitter is 12.9 ps at 1 GHz. The measured operation frequency range is from 0.8 GHz to 1.2 GHz.

AB - An all-digital fast-locked synchronous duty-cycle corrector is presented. It corrects the duty cycle and synchronizes the input and output clocks in 10 clock cycles. The proposed circuit has been fabricated in a 0.18- μ m CMOS technology. The measured duty-cycle error is between 1.5% and —1.4% for the input duty cycle of 40% ~ 60%. The measured peak-to-peak jitter is 12.9 ps at 1 GHz. The measured operation frequency range is from 0.8 GHz to 1.2 GHz.

KW - All-digital

KW - duty-cycle corrector (DCC)

KW - fast-locked

UR - https://www.scopus.com/pages/publications/33947422477

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JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 12

ER -

All-Digital Fast-Locked Synchronous Duty-Cycle Corrector

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Keywords

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