An accurate MOS transistor model for submicron VLSI circuits--BSIM_plus

Sudhir M. Gowda*, Bing J. Sheu, James S. Cable

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

An accurate MOS transistor model that is suitable for the simulation of analog and digital circuits with deep submicron channel-length transistors is presented. The BSIM_plus model uses a compact set of device physics-based parameters. Continuity of the drain current and derivatives in the subthreshold, linear, and saturation regions of operation has been achieved. A novel geometric dependence scheme allows consistent simulation of transistors over the entire design space. Experimental results on NMOS and PMOS transistors with effective channel lengths down to 0.15 μm are presented.

Original languageEnglish
Title of host publicationProceedings of the Custom Integrated Circuits Conference
PublisherPubl by IEEE
ISBN (Print)0780300157
StatePublished - 1991
Externally publishedYes
EventProceedings of the IEEE 1991 Custom Integrated Circuits Conference - San Diego, CA, USA
Duration: 12 05 199115 05 1991

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Conference

ConferenceProceedings of the IEEE 1991 Custom Integrated Circuits Conference
CitySan Diego, CA, USA
Period12/05/9115/05/91

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