An adaptive high-speed vector quantization

Oscal T.C. Chen; Zhen Zhang; Bing J. Sheu

doi:10.1109/VLSISP.1992.641053

An adaptive high-speed vector quantization

Oscal T.C. Chen, Zhen Zhang, Bing J. Sheu

University of Southern California

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

An adaptive method for vector quantization and the associated VLSI architecture are presented. This method does not require apriori knowledge of the source statistics and codebook training. The codebook is generated on the fly and is constantly updated to capture local textual features of data. The algorithm is shown to reach rate distortion function for memoryless sources. We also propose a computation architecture which consists of two move-to-front vector quantizers and an index generator. The processing element in the move-to-front vector quantizer is designed by using a 0.5 μm CMOS technology. The total transistor count can be about 10,000. It can provide a computing capability of 200M pixels per second for high-speed image compression systems. By using this method, a high-speed VLSI processor with good local adaptivity, reduced complexity, and fairly good compression ratio can be achieved.

Original language	English
Title of host publication	Workshop on VLSI Signal Processing 1992
Editors	Wojtek Przytula, Kung Yao, Rajeev Jain, Jan Rabaey
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	205-214
Number of pages	10
ISBN (Electronic)	0780308115, 9780780308114
DOIs	https://doi.org/10.1109/VLSISP.1992.641053
State	Published - 1992
Externally published	Yes
Event	6th IEEE Workshop on VLSI Signal Processing - Los Angeles, United States Duration: 28 10 1992 → 30 10 1992

Publication series

Name	Workshop on VLSI Signal Processing 1992

Conference

Conference	6th IEEE Workshop on VLSI Signal Processing
Country/Territory	United States
City	Los Angeles
Period	28/10/92 → 30/10/92

Bibliographical note

Publisher Copyright:
© 1992 IEEE.

Access to Document

10.1109/VLSISP.1992.641053

Cite this

@inproceedings{c0e7c5911e5b49b89b75246a5beaaee0,

title = "An adaptive high-speed vector quantization",

abstract = "An adaptive method for vector quantization and the associated VLSI architecture are presented. This method does not require apriori knowledge of the source statistics and codebook training. The codebook is generated on the fly and is constantly updated to capture local textual features of data. The algorithm is shown to reach rate distortion function for memoryless sources. We also propose a computation architecture which consists of two move-to-front vector quantizers and an index generator. The processing element in the move-to-front vector quantizer is designed by using a 0.5 μm CMOS technology. The total transistor count can be about 10,000. It can provide a computing capability of 200M pixels per second for high-speed image compression systems. By using this method, a high-speed VLSI processor with good local adaptivity, reduced complexity, and fairly good compression ratio can be achieved.",

author = "Chen, {Oscal T.C.} and Zhen Zhang and Sheu, {Bing J.}",

note = "Publisher Copyright: {\textcopyright} 1992 IEEE.; 6th IEEE Workshop on VLSI Signal Processing ; Conference date: 28-10-1992 Through 30-10-1992",

year = "1992",

doi = "10.1109/VLSISP.1992.641053",

language = "英语",

series = "Workshop on VLSI Signal Processing 1992",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "205--214",

editor = "Wojtek Przytula and Kung Yao and Rajeev Jain and Jan Rabaey",

booktitle = "Workshop on VLSI Signal Processing 1992",

address = "美国",

}

Chen, OTC, Zhang, Z & Sheu, BJ 1992, An adaptive high-speed vector quantization. in W Przytula, K Yao, R Jain & J Rabaey (eds), Workshop on VLSI Signal Processing 1992., 641053, Workshop on VLSI Signal Processing 1992, Institute of Electrical and Electronics Engineers Inc., pp. 205-214, 6th IEEE Workshop on VLSI Signal Processing, Los Angeles, United States, 28/10/92. https://doi.org/10.1109/VLSISP.1992.641053

An adaptive high-speed vector quantization. / Chen, Oscal T.C.; Zhang, Zhen; Sheu, Bing J.
Workshop on VLSI Signal Processing 1992. ed. / Wojtek Przytula; Kung Yao; Rajeev Jain; Jan Rabaey. Institute of Electrical and Electronics Engineers Inc., 1992. p. 205-214 641053 (Workshop on VLSI Signal Processing 1992).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - An adaptive high-speed vector quantization

AU - Chen, Oscal T.C.

AU - Zhang, Zhen

AU - Sheu, Bing J.

PY - 1992

Y1 - 1992

N2 - An adaptive method for vector quantization and the associated VLSI architecture are presented. This method does not require apriori knowledge of the source statistics and codebook training. The codebook is generated on the fly and is constantly updated to capture local textual features of data. The algorithm is shown to reach rate distortion function for memoryless sources. We also propose a computation architecture which consists of two move-to-front vector quantizers and an index generator. The processing element in the move-to-front vector quantizer is designed by using a 0.5 μm CMOS technology. The total transistor count can be about 10,000. It can provide a computing capability of 200M pixels per second for high-speed image compression systems. By using this method, a high-speed VLSI processor with good local adaptivity, reduced complexity, and fairly good compression ratio can be achieved.

AB - An adaptive method for vector quantization and the associated VLSI architecture are presented. This method does not require apriori knowledge of the source statistics and codebook training. The codebook is generated on the fly and is constantly updated to capture local textual features of data. The algorithm is shown to reach rate distortion function for memoryless sources. We also propose a computation architecture which consists of two move-to-front vector quantizers and an index generator. The processing element in the move-to-front vector quantizer is designed by using a 0.5 μm CMOS technology. The total transistor count can be about 10,000. It can provide a computing capability of 200M pixels per second for high-speed image compression systems. By using this method, a high-speed VLSI processor with good local adaptivity, reduced complexity, and fairly good compression ratio can be achieved.

UR - http://www.scopus.com/inward/record.url?scp=85068163822&partnerID=8YFLogxK

U2 - 10.1109/VLSISP.1992.641053

DO - 10.1109/VLSISP.1992.641053

M3 - 会议稿件

AN - SCOPUS:85068163822

T3 - Workshop on VLSI Signal Processing 1992

SP - 205

EP - 214

BT - Workshop on VLSI Signal Processing 1992

A2 - Przytula, Wojtek

A2 - Yao, Kung

A2 - Jain, Rajeev

A2 - Rabaey, Jan

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 6th IEEE Workshop on VLSI Signal Processing

Y2 - 28 October 1992 through 30 October 1992

ER -

An adaptive high-speed vector quantization

Abstract

Publication series

Conference

Bibliographical note

Access to Document

Other files and links

Fingerprint

Cite this