An all-digital duty cycle corrector

Bo Jiun Chen; Shao Ku Kao; Shen Iuan Liu

doi:10.1109/VDAT.2006.258158

An all-digital duty cycle corrector

Bo Jiun Chen^*
, Shao Ku Kao
, Shen Iuan Liu

^*Corresponding author for this work

National Taiwan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

An all-digital 50% duty cycle corrector (DCC) is presented. The features of the proposed DCC include a wide operation frequency range, a wide input duty cycle range for the input clock, and a short locked time to recover the duty cycle of 50%. This digital DCC has been implemented in a 0.35μm 2P4M CMOS process. The acceptable duty cycle and frequency range of the input clock is 25%-75% and 250MHz-600MHz, respectively. The measured peak-peak jitter is 1.7.3ps at 600MHz, Besides, this DCC saves the power consumption by turning off a half delay line. Its power consumption is 16mW at 600MHz.

Original language	English
Title of host publication	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers
Pages	195-198
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2006.258158
State	Published - 2007
Externally published	Yes
Event	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Hsinchu, Taiwan Duration: 26 04 2007 → 28 04 2007

Publication series

Name	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

Conference

Conference	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006
Country/Territory	Taiwan
City	Hsinchu
Period	26/04/07 → 28/04/07

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10.1109/VDAT.2006.258158

Cite this

Chen, B. J., Kao, S. K., & Liu, S. I. (2007). An all-digital duty cycle corrector. In 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers (pp. 195-198). Article 4027530 (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers). https://doi.org/10.1109/VDAT.2006.258158

@inproceedings{d1574d0098ee40bab11ef2b46996f76a,

title = "An all-digital duty cycle corrector",

abstract = "An all-digital 50\% duty cycle corrector (DCC) is presented. The features of the proposed DCC include a wide operation frequency range, a wide input duty cycle range for the input clock, and a short locked time to recover the duty cycle of 50\%. This digital DCC has been implemented in a 0.35μm 2P4M CMOS process. The acceptable duty cycle and frequency range of the input clock is 25\%-75\% and 250MHz-600MHz, respectively. The measured peak-peak jitter is 1.7.3ps at 600MHz, Besides, this DCC saves the power consumption by turning off a half delay line. Its power consumption is 16mW at 600MHz.",

author = "Chen, \{Bo Jiun\} and Kao, \{Shao Ku\} and Liu, \{Shen Iuan\}",

year = "2007",

doi = "10.1109/VDAT.2006.258158",

language = "英语",

isbn = "1424401798",

series = "2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers",

pages = "195--198",

booktitle = "2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers",

note = "2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 ; Conference date: 26-04-2007 Through 28-04-2007",

}

Chen, BJ, Kao, SK & Liu, SI 2007, An all-digital duty cycle corrector. in 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers., 4027530, 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers, pp. 195-198, 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006, Hsinchu, Taiwan, 26/04/07. https://doi.org/10.1109/VDAT.2006.258158

An all-digital duty cycle corrector. / Chen, Bo Jiun; Kao, Shao Ku; Liu, Shen Iuan.
2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. p. 195-198 4027530 (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Chen, Bo Jiun

AU - Kao, Shao Ku

AU - Liu, Shen Iuan

PY - 2007

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N2 - An all-digital 50% duty cycle corrector (DCC) is presented. The features of the proposed DCC include a wide operation frequency range, a wide input duty cycle range for the input clock, and a short locked time to recover the duty cycle of 50%. This digital DCC has been implemented in a 0.35μm 2P4M CMOS process. The acceptable duty cycle and frequency range of the input clock is 25%-75% and 250MHz-600MHz, respectively. The measured peak-peak jitter is 1.7.3ps at 600MHz, Besides, this DCC saves the power consumption by turning off a half delay line. Its power consumption is 16mW at 600MHz.

AB - An all-digital 50% duty cycle corrector (DCC) is presented. The features of the proposed DCC include a wide operation frequency range, a wide input duty cycle range for the input clock, and a short locked time to recover the duty cycle of 50%. This digital DCC has been implemented in a 0.35μm 2P4M CMOS process. The acceptable duty cycle and frequency range of the input clock is 25%-75% and 250MHz-600MHz, respectively. The measured peak-peak jitter is 1.7.3ps at 600MHz, Besides, this DCC saves the power consumption by turning off a half delay line. Its power consumption is 16mW at 600MHz.

UR - https://www.scopus.com/pages/publications/34748813723

U2 - 10.1109/VDAT.2006.258158

DO - 10.1109/VDAT.2006.258158

M3 - 会议稿件

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SN - 1424401798

SN - 9781424401796

T3 - 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

SP - 195

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BT - 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

T2 - 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006

Y2 - 26 April 2007 through 28 April 2007

ER -

An all-digital duty cycle corrector

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