Abstract
The building blocks of a self-organizing analog neural chip are shown. Its function is to evaluate the large number of dot products of the given input vectors and the stored weight vectors in a fully parallel format. Lateral competition is to be performed among the analog output voltages and the neural unit with the largest voltage level is to emerge as a single winner. Updating synapse weights is performed in a digital signal processor using an unsupervised learning rule. Design considerations addressed in the construction of the WTA (winner-take-all) circuit are: high resolution, fast operation, and layout compactness. The 4-MHz analog neural network processor chip, fabricated in a 2μm CMOS process, contains 25 neurons in the input layer and 64 neurons in the competitive layer. The behavior of the WTA circuit with only one winner for a lossy image data compression application is shown.
Original language | English |
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Title of host publication | Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 136-137 |
Number of pages | 2 |
ISBN (Electronic) | 0780305736 |
DOIs | |
State | Published - 1992 |
Externally published | Yes |
Event | 39th IEEE International Solid-State Circuits Conference, ISSCC 1992 - San Francisco, United States Duration: 19 02 1992 → 21 02 1992 |
Publication series
Name | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |
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Volume | 1992-February |
ISSN (Print) | 0193-6530 |
Conference
Conference | 39th IEEE International Solid-State Circuits Conference, ISSCC 1992 |
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Country/Territory | United States |
City | San Francisco |
Period | 19/02/92 → 21/02/92 |
Bibliographical note
Publisher Copyright:© 1992 IEEE.