An analog neural network processor for self-organizing mapping

Bing J. Sheu; Joongho Choi; Chia Fen Chang

doi:10.1109/ISSCC.1992.200449

An analog neural network processor for self-organizing mapping

Bing J. Sheu
, Joongho Choi
, Chia Fen Chang

University of Southern California

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

10 Scopus citations

Abstract

The building blocks of a self-organizing analog neural chip are shown. Its function is to evaluate the large number of dot products of the given input vectors and the stored weight vectors in a fully parallel format. Lateral competition is to be performed among the analog output voltages and the neural unit with the largest voltage level is to emerge as a single winner. Updating synapse weights is performed in a digital signal processor using an unsupervised learning rule. Design considerations addressed in the construction of the WTA (winner-take-all) circuit are: high resolution, fast operation, and layout compactness. The 4-MHz analog neural network processor chip, fabricated in a 2μm CMOS process, contains 25 neurons in the input layer and 64 neurons in the competitive layer. The behavior of the WTA circuit with only one winner for a lossy image data compression application is shown.

Original language	English
Title of host publication	Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	136-137
Number of pages	2
ISBN (Electronic)	0780305736
DOIs	https://doi.org/10.1109/ISSCC.1992.200449
State	Published - 1992
Externally published	Yes
Event	39th IEEE International Solid-State Circuits Conference, ISSCC 1992 - San Francisco, United States Duration: 19 02 1992 → 21 02 1992

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	1992-February
ISSN (Print)	0193-6530

Conference

Conference	39th IEEE International Solid-State Circuits Conference, ISSCC 1992
Country/Territory	United States
City	San Francisco
Period	19/02/92 → 21/02/92

Bibliographical note

Publisher Copyright:
© 1992 IEEE.

Access to Document

10.1109/ISSCC.1992.200449

Cite this

Sheu, B. J., Choi, J., & Chang, C. F. (1992). An analog neural network processor for self-organizing mapping. In Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992 (pp. 136-137). Article 200449 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 1992-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.1992.200449

Sheu, Bing J. ; Choi, Joongho ; Chang, Chia Fen. / An analog neural network processor for self-organizing mapping. Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992. Institute of Electrical and Electronics Engineers Inc., 1992. pp. 136-137 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

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title = "An analog neural network processor for self-organizing mapping",

abstract = "The building blocks of a self-organizing analog neural chip are shown. Its function is to evaluate the large number of dot products of the given input vectors and the stored weight vectors in a fully parallel format. Lateral competition is to be performed among the analog output voltages and the neural unit with the largest voltage level is to emerge as a single winner. Updating synapse weights is performed in a digital signal processor using an unsupervised learning rule. Design considerations addressed in the construction of the WTA (winner-take-all) circuit are: high resolution, fast operation, and layout compactness. The 4-MHz analog neural network processor chip, fabricated in a 2μm CMOS process, contains 25 neurons in the input layer and 64 neurons in the competitive layer. The behavior of the WTA circuit with only one winner for a lossy image data compression application is shown.",

author = "Sheu, \{Bing J.\} and Joongho Choi and Chang, \{Chia Fen\}",

note = "Publisher Copyright: {\textcopyright} 1992 IEEE.; 39th IEEE International Solid-State Circuits Conference, ISSCC 1992 ; Conference date: 19-02-1992 Through 21-02-1992",

year = "1992",

doi = "10.1109/ISSCC.1992.200449",

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series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

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Sheu, BJ, Choi, J & Chang, CF 1992, An analog neural network processor for self-organizing mapping. in Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992., 200449, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 1992-February, Institute of Electrical and Electronics Engineers Inc., pp. 136-137, 39th IEEE International Solid-State Circuits Conference, ISSCC 1992, San Francisco, United States, 19/02/92. https://doi.org/10.1109/ISSCC.1992.200449

An analog neural network processor for self-organizing mapping. / Sheu, Bing J.; Choi, Joongho; Chang, Chia Fen.
Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992. Institute of Electrical and Electronics Engineers Inc., 1992. p. 136-137 200449 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 1992-February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Sheu BJ, Choi J, Chang CF. An analog neural network processor for self-organizing mapping. In Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992. Institute of Electrical and Electronics Engineers Inc. 1992. p. 136-137. 200449. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.1992.200449

An analog neural network processor for self-organizing mapping

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