An analog VLSI edge detection chip and digital multiprocessor chip for neural-based vision processing

Hiroto Okada; Bing J. Sheu; Chia Fen Chang

doi:10.1109/ICSYSE.1992.236882

An analog VLSI edge detection chip and digital multiprocessor chip for neural-based vision processing

Hiroto Okada, Bing J. Sheu, Chia Fen Chang

University of Southern California

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper describes a mixed-signal VLSI design for early vision processing, which includes an analog edge detection chip with embedded array photosensors and a digital multi-processor chip. The system architecture overview shows the combination of the analog chip and the digital processors can perform high efficient processing in the neural-based vision processing. The analog edge detection chip consisting of 258 × 258 photosensor cells can be implemented in an area of 13.5 × 15.5 mm² using the new MOSIS 0.8 μm CMOS technology. The digital multi-processor chip which includes sixty four processing elements can be implemented in a 15.0 × 18.0 mm² chip using a industrial-scale 0.5 μm CMOS technology from TRW, Inc. A system implementation for fingerprint verification is presented as an example of possible applications.

Original language	English
Title of host publication	Proceedings of the IEEE International Conference on Systems Engineering
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	361-364
Number of pages	4
ISBN (Electronic)	0780307348, 9780780307346
DOIs	https://doi.org/10.1109/ICSYSE.1992.236882
State	Published - 1992
Externally published	Yes
Event	1992 IEEE International Conference on Systems Engineering - Kobe, Japan Duration: 17 09 1992 → 19 09 1992

Publication series

Name	Proceedings of the IEEE International Conference on Systems Engineering

Conference

Conference	1992 IEEE International Conference on Systems Engineering
Country/Territory	Japan
City	Kobe
Period	17/09/92 → 19/09/92

Bibliographical note

Publisher Copyright:
© 1992 IEEE.

Access to Document

10.1109/ICSYSE.1992.236882

Cite this

Okada, H., Sheu, B. J., & Chang, C. F. (1992). An analog VLSI edge detection chip and digital multiprocessor chip for neural-based vision processing. In Proceedings of the IEEE International Conference on Systems Engineering (pp. 361-364). Article 236882 (Proceedings of the IEEE International Conference on Systems Engineering). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICSYSE.1992.236882

Okada, Hiroto ; Sheu, Bing J. ; Chang, Chia Fen. / An analog VLSI edge detection chip and digital multiprocessor chip for neural-based vision processing. Proceedings of the IEEE International Conference on Systems Engineering. Institute of Electrical and Electronics Engineers Inc., 1992. pp. 361-364 (Proceedings of the IEEE International Conference on Systems Engineering).

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title = "An analog VLSI edge detection chip and digital multiprocessor chip for neural-based vision processing",

abstract = "This paper describes a mixed-signal VLSI design for early vision processing, which includes an analog edge detection chip with embedded array photosensors and a digital multi-processor chip. The system architecture overview shows the combination of the analog chip and the digital processors can perform high efficient processing in the neural-based vision processing. The analog edge detection chip consisting of 258 × 258 photosensor cells can be implemented in an area of 13.5 × 15.5 mm2 using the new MOSIS 0.8 μm CMOS technology. The digital multi-processor chip which includes sixty four processing elements can be implemented in a 15.0 × 18.0 mm2 chip using a industrial-scale 0.5 μm CMOS technology from TRW, Inc. A system implementation for fingerprint verification is presented as an example of possible applications.",

author = "Hiroto Okada and Sheu, {Bing J.} and Chang, {Chia Fen}",

note = "Publisher Copyright: {\textcopyright} 1992 IEEE.; 1992 IEEE International Conference on Systems Engineering ; Conference date: 17-09-1992 Through 19-09-1992",

year = "1992",

doi = "10.1109/ICSYSE.1992.236882",

language = "英语",

series = "Proceedings of the IEEE International Conference on Systems Engineering",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "361--364",

booktitle = "Proceedings of the IEEE International Conference on Systems Engineering",

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Okada, H, Sheu, BJ & Chang, CF 1992, An analog VLSI edge detection chip and digital multiprocessor chip for neural-based vision processing. in Proceedings of the IEEE International Conference on Systems Engineering., 236882, Proceedings of the IEEE International Conference on Systems Engineering, Institute of Electrical and Electronics Engineers Inc., pp. 361-364, 1992 IEEE International Conference on Systems Engineering, Kobe, Japan, 17/09/92. https://doi.org/10.1109/ICSYSE.1992.236882

An analog VLSI edge detection chip and digital multiprocessor chip for neural-based vision processing. / Okada, Hiroto; Sheu, Bing J.; Chang, Chia Fen.
Proceedings of the IEEE International Conference on Systems Engineering. Institute of Electrical and Electronics Engineers Inc., 1992. p. 361-364 236882 (Proceedings of the IEEE International Conference on Systems Engineering).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper describes a mixed-signal VLSI design for early vision processing, which includes an analog edge detection chip with embedded array photosensors and a digital multi-processor chip. The system architecture overview shows the combination of the analog chip and the digital processors can perform high efficient processing in the neural-based vision processing. The analog edge detection chip consisting of 258 × 258 photosensor cells can be implemented in an area of 13.5 × 15.5 mm2 using the new MOSIS 0.8 μm CMOS technology. The digital multi-processor chip which includes sixty four processing elements can be implemented in a 15.0 × 18.0 mm2 chip using a industrial-scale 0.5 μm CMOS technology from TRW, Inc. A system implementation for fingerprint verification is presented as an example of possible applications.

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Okada H, Sheu BJ, Chang CF. An analog VLSI edge detection chip and digital multiprocessor chip for neural-based vision processing. In Proceedings of the IEEE International Conference on Systems Engineering. Institute of Electrical and Electronics Engineers Inc. 1992. p. 361-364. 236882. (Proceedings of the IEEE International Conference on Systems Engineering). doi: 10.1109/ICSYSE.1992.236882

An analog VLSI edge detection chip and digital multiprocessor chip for neural-based vision processing

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