An area-efficient carry select adder design by sharing the common boolean logic term

I. Chyn Wey*, Cheng Chen Ho, Yi Sheng Lin, Chien Chang Peng

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

22 Scopus citations

Abstract

In this paper, we proposed an area-efficient carry select adder by sharing the common Boolean logic term. After logic simplification and sharing partial circuit, we only need one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation. Through the multiplexer, we can select the correct output result according to the logic state of carry-in signal. In this way, the transistor count in a 32-bit carry select adder can be greatly reduced from 1947 to 960. Moreover, the power consumption can be reduced from 1.26mw to 0.37mw as well as power delay product reduced from 2.14mw*ns to 1.28mw*ns.

Original languageEnglish
Title of host publicationInternational MultiConference of Engineers and Computer Scientists, IMECS 2012
PublisherNewswood Limited
Pages1091-1094
Number of pages4
ISBN (Print)9789881925190
StatePublished - 2012
Event2012 International MultiConference of Engineers and Computer Scientists, IMECS 2012 - Kowloon, Hong Kong
Duration: 14 03 201216 03 2012

Publication series

NameLecture Notes in Engineering and Computer Science
Volume2196
ISSN (Print)2078-0958

Conference

Conference2012 International MultiConference of Engineers and Computer Scientists, IMECS 2012
Country/TerritoryHong Kong
CityKowloon
Period14/03/1216/03/12

Keywords

  • Area-Efficient
  • Boolean Logic
  • Carry Select Adder
  • Hardware-Sharing

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