An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on Belief Propagation

Huifei Rao; Jie Chen; Vicky H. Zhao; Woon Tiong Ang; I. Chyn Wey; An Yeu Wu

doi:10.1109/ISCAS.2008.4541491

An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on Belief Propagation

Huifei Rao^*, Jie Chen, Vicky H. Zhao, Woon Tiong Ang, I. Chyn Wey, An Yeu Wu

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

As silicon circuits quickly approach their physical limitations, researchers are actively looking for novel building blocks to develop nanocircuits. However, future nanoelectronic circuits are more error-prone than conventional CMOS designs because of their self-assembly design. To help design fault-tolerant nanoscale circuits, new circuit design and testing tools are needed. In this paper, an efficient methodology to evaluate nanoscale circuit fault tolerance based on Belief Propagation (BP) algorithm is proposed. Compared with existing approaches, the BP algorithm is more efficient in terms of memory requirements and CPU times. The proposed methodology can be easily run on multiple CPUs to achieve parallel processing and thus further reduces simulation time.

Original language	English
Title of host publication	2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Pages	608-611
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2008.4541491
State	Published - 2008
Externally published	Yes
Event	2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, United States Duration: 18 05 2008 → 21 05 2008

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Country/Territory	United States
City	Seattle, WA
Period	18/05/08 → 21/05/08

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10.1109/ISCAS.2008.4541491

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Rao, H., Chen, J., Zhao, V. H., Ang, W. T., Wey, I. C., & Wu, A. Y. (2008). An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on Belief Propagation. In 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 (pp. 608-611). Article 4541491 (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2008.4541491

@inproceedings{c4403dfa0a0b4005bc84635c4d83f983,

title = "An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on Belief Propagation",

abstract = "As silicon circuits quickly approach their physical limitations, researchers are actively looking for novel building blocks to develop nanocircuits. However, future nanoelectronic circuits are more error-prone than conventional CMOS designs because of their self-assembly design. To help design fault-tolerant nanoscale circuits, new circuit design and testing tools are needed. In this paper, an efficient methodology to evaluate nanoscale circuit fault tolerance based on Belief Propagation (BP) algorithm is proposed. Compared with existing approaches, the BP algorithm is more efficient in terms of memory requirements and CPU times. The proposed methodology can be easily run on multiple CPUs to achieve parallel processing and thus further reduces simulation time.",

author = "Huifei Rao and Jie Chen and Zhao, \{Vicky H.\} and Ang, \{Woon Tiong\} and Wey, \{I. Chyn\} and Wu, \{An Yeu\}",

year = "2008",

doi = "10.1109/ISCAS.2008.4541491",

language = "英语",

isbn = "9781424416844",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "608--611",

booktitle = "2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008",

note = "2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 ; Conference date: 18-05-2008 Through 21-05-2008",

}

Rao, H, Chen, J, Zhao, VH, Ang, WT, Wey, IC & Wu, AY 2008, An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on Belief Propagation. in 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008., 4541491, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 608-611, 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008, Seattle, WA, United States, 18/05/08. https://doi.org/10.1109/ISCAS.2008.4541491

An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on Belief Propagation. / Rao, Huifei; Chen, Jie; Zhao, Vicky H. et al.
2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008. 2008. p. 608-611 4541491 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Wey, I. Chyn

AU - Wu, An Yeu

PY - 2008

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AB - As silicon circuits quickly approach their physical limitations, researchers are actively looking for novel building blocks to develop nanocircuits. However, future nanoelectronic circuits are more error-prone than conventional CMOS designs because of their self-assembly design. To help design fault-tolerant nanoscale circuits, new circuit design and testing tools are needed. In this paper, an efficient methodology to evaluate nanoscale circuit fault tolerance based on Belief Propagation (BP) algorithm is proposed. Compared with existing approaches, the BP algorithm is more efficient in terms of memory requirements and CPU times. The proposed methodology can be easily run on multiple CPUs to achieve parallel processing and thus further reduces simulation time.

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SN - 9781424416844

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

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BT - 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008

T2 - 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008

Y2 - 18 May 2008 through 21 May 2008

ER -

An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on Belief Propagation

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