Abstract
Achieving a high decoding throughput using a successive cancellation list (SCL) decoder for polar codes is difficult due to its sequential decoding architecture. In this work, combining the local sorter from a single parity check (SPC) node with a shift-based path memory, a modified fast simplified successive cancellation list (Fast-SSCL) decoder is proposed, in order to provide a high-throughput using a low-complexity implementation. The proposed modified Fast-SSCL decoder can be operated at 470 MHz and was synthesized with an area of 5.26 mm2 using a TSMC 90 nm CMOS process. The decoder presented in this work is able to improve the throughput to area ratio (TAR) by more than 30% compared with the previous designs.
| Original language | English |
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| Title of host publication | 2019 IEEE International Conference on Communications Workshops, ICC Workshops 2019 - Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781728123738 |
| DOIs | |
| State | Published - 05 2019 |
| Event | 2019 IEEE International Conference on Communications Workshops, ICC Workshops 2019 - Shanghai, China Duration: 20 05 2019 → 24 05 2019 |
Publication series
| Name | 2019 IEEE International Conference on Communications Workshops, ICC Workshops 2019 - Proceedings |
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Conference
| Conference | 2019 IEEE International Conference on Communications Workshops, ICC Workshops 2019 |
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| Country/Territory | China |
| City | Shanghai |
| Period | 20/05/19 → 24/05/19 |
Bibliographical note
Publisher Copyright:© 2019 IEEE.
Keywords
- Hardware implementation
- Polar codes
- Successive cancellation list decoding