An FPGA architecture design of parameter-adaptive real-time image processing system for edge detection

Pei Yung Hsiao; Le Tien Li; Chia Hsiung Chen; Szi Wen Chen; Sao Jie Chen

doi:10.1109/EITC.2005.1544366

An FPGA architecture design of parameter-adaptive real-time image processing system for edge detection

Pei Yung Hsiao^*, Le Tien Li, Chia Hsiung Chen, Szi Wen Chen, Sao Jie Chen

^*Corresponding author for this work

Department of Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

12 Scopus citations

Abstract

In this paper we present an FPGA architecture design of parameter-adaptive real-time image processing system for edge detection. The system contains two edge detection algorithms which are suitable for hardware realization and insensitive to noise. The two adopted algorithms are able to produce different outputs suitable for different applications. A controller which integrates parameter setting, continuous edge detection task processing and output selection is proposed. The proposed modified LGT algorithm not only preserves the original edge detection performance, but also greatly reduces the use of hardware resource. We adopt FPGA design flow as our early-stage verification platform, and result in a maximum working frequency of 54MHz, which is able to process 205 512×512 grayscale images, and is 90 times faster than the software execution.

Original language	English
Title of host publication	Emerging Information Technology Conference 2005
Pages	130-132
Number of pages	3
DOIs	https://doi.org/10.1109/EITC.2005.1544366
State	Published - 2005
Event	Emerging Information Technology Conference 2005 - Taipei, Taiwan Duration: 15 08 2005 → 16 08 2005

Publication series

Name	Emerging Information Technology Conference 2005
Volume	2005

Conference

Conference	Emerging Information Technology Conference 2005
Country/Territory	Taiwan
City	Taipei
Period	15/08/05 → 16/08/05

Access to Document

10.1109/EITC.2005.1544366

Cite this

@inproceedings{ada1a5bf9f31497d881371ec7db1a8bd,

title = "An FPGA architecture design of parameter-adaptive real-time image processing system for edge detection",

abstract = "In this paper we present an FPGA architecture design of parameter-adaptive real-time image processing system for edge detection. The system contains two edge detection algorithms which are suitable for hardware realization and insensitive to noise. The two adopted algorithms are able to produce different outputs suitable for different applications. A controller which integrates parameter setting, continuous edge detection task processing and output selection is proposed. The proposed modified LGT algorithm not only preserves the original edge detection performance, but also greatly reduces the use of hardware resource. We adopt FPGA design flow as our early-stage verification platform, and result in a maximum working frequency of 54MHz, which is able to process 205 512×512 grayscale images, and is 90 times faster than the software execution.",

author = "Hsiao, \{Pei Yung\} and Li, \{Le Tien\} and Chen, \{Chia Hsiung\} and Chen, \{Szi Wen\} and Chen, \{Sao Jie\}",

year = "2005",

doi = "10.1109/EITC.2005.1544366",

language = "英语",

isbn = "0780393295",

series = "Emerging Information Technology Conference 2005",

pages = "130--132",

booktitle = "Emerging Information Technology Conference 2005",

note = "Emerging Information Technology Conference 2005 ; Conference date: 15-08-2005 Through 16-08-2005",

}

Hsiao, PY, Li, LT, Chen, CH, Chen, SW & Chen, SJ 2005, An FPGA architecture design of parameter-adaptive real-time image processing system for edge detection. in Emerging Information Technology Conference 2005., 1544366, Emerging Information Technology Conference 2005, vol. 2005, pp. 130-132, Emerging Information Technology Conference 2005, Taipei, Taiwan, 15/08/05. https://doi.org/10.1109/EITC.2005.1544366

An FPGA architecture design of parameter-adaptive real-time image processing system for edge detection. / Hsiao, Pei Yung; Li, Le Tien; Chen, Chia Hsiung et al.
Emerging Information Technology Conference 2005. 2005. p. 130-132 1544366 (Emerging Information Technology Conference 2005; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - An FPGA architecture design of parameter-adaptive real-time image processing system for edge detection

AU - Hsiao, Pei Yung

AU - Li, Le Tien

AU - Chen, Chia Hsiung

AU - Chen, Szi Wen

AU - Chen, Sao Jie

PY - 2005

Y1 - 2005

N2 - In this paper we present an FPGA architecture design of parameter-adaptive real-time image processing system for edge detection. The system contains two edge detection algorithms which are suitable for hardware realization and insensitive to noise. The two adopted algorithms are able to produce different outputs suitable for different applications. A controller which integrates parameter setting, continuous edge detection task processing and output selection is proposed. The proposed modified LGT algorithm not only preserves the original edge detection performance, but also greatly reduces the use of hardware resource. We adopt FPGA design flow as our early-stage verification platform, and result in a maximum working frequency of 54MHz, which is able to process 205 512×512 grayscale images, and is 90 times faster than the software execution.

AB - In this paper we present an FPGA architecture design of parameter-adaptive real-time image processing system for edge detection. The system contains two edge detection algorithms which are suitable for hardware realization and insensitive to noise. The two adopted algorithms are able to produce different outputs suitable for different applications. A controller which integrates parameter setting, continuous edge detection task processing and output selection is proposed. The proposed modified LGT algorithm not only preserves the original edge detection performance, but also greatly reduces the use of hardware resource. We adopt FPGA design flow as our early-stage verification platform, and result in a maximum working frequency of 54MHz, which is able to process 205 512×512 grayscale images, and is 90 times faster than the software execution.

UR - https://www.scopus.com/pages/publications/33751181227

U2 - 10.1109/EITC.2005.1544366

DO - 10.1109/EITC.2005.1544366

M3 - 会议稿件

AN - SCOPUS:33751181227

SN - 0780393295

SN - 9780780393295

T3 - Emerging Information Technology Conference 2005

SP - 130

EP - 132

BT - Emerging Information Technology Conference 2005

T2 - Emerging Information Technology Conference 2005

Y2 - 15 August 2005 through 16 August 2005

ER -

An FPGA architecture design of parameter-adaptive real-time image processing system for edge detection

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this