Abstract
A previous study shows that a low-density parity-check (LDPC) coded modulation scheme with an extremely sparse parity-check matrix and non-Gray mapping is able to achieve an error-rate performance compatible to that of a conventional Gray-mapping based scheme. This paper presents an associated iterative demodulation and decoding (IDD) receiver architecture that is targeted at flash memory applications. By adopting this extremely spare LDPC code, both the storage and the computational complexity of the decoder are lowered. The complexity of demodulator is also reduced by using the proposed simplified method. Moreover, a two-codeword scheduling approach is used so as to minimize the idles and, hence, a high throughput can be achieved. Compared to the conventional Gray-based scheme, the proposed scheme provides a similar error performance and a better hardware efficiency.
Original language | English |
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Title of host publication | 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 289-292 |
Number of pages | 4 |
ISBN (Electronic) | 9781509015702 |
DOIs | |
State | Published - 03 01 2017 |
Event | 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 - Jeju, Korea, Republic of Duration: 25 10 2016 → 28 10 2016 |
Publication series
Name | 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 |
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Conference
Conference | 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 |
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Country/Territory | Korea, Republic of |
City | Jeju |
Period | 25/10/16 → 28/10/16 |
Bibliographical note
Publisher Copyright:© 2016 IEEE.
Keywords
- Flash memory
- LDPC codes
- coded modulation
- iterative demodulation and decoding (IDD)