An IDD receiver of LDPC coded modulation scheme for flash memory applications

Mao Ruei Li, Ting Yu Kuan, Huang Chang Lee, Yeong Luh Ueng

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

A previous study shows that a low-density parity-check (LDPC) coded modulation scheme with an extremely sparse parity-check matrix and non-Gray mapping is able to achieve an error-rate performance compatible to that of a conventional Gray-mapping based scheme. This paper presents an associated iterative demodulation and decoding (IDD) receiver architecture that is targeted at flash memory applications. By adopting this extremely spare LDPC code, both the storage and the computational complexity of the decoder are lowered. The complexity of demodulator is also reduced by using the proposed simplified method. Moreover, a two-codeword scheduling approach is used so as to minimize the idles and, hence, a high throughput can be achieved. Compared to the conventional Gray-based scheme, the proposed scheme provides a similar error performance and a better hardware efficiency.

Original languageEnglish
Title of host publication2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages289-292
Number of pages4
ISBN (Electronic)9781509015702
DOIs
StatePublished - 03 01 2017
Event2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 - Jeju, Korea, Republic of
Duration: 25 10 201628 10 2016

Publication series

Name2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016

Conference

Conference2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
Country/TerritoryKorea, Republic of
CityJeju
Period25/10/1628/10/16

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

Keywords

  • Flash memory
  • LDPC codes
  • coded modulation
  • iterative demodulation and decoding (IDD)

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