An investigation into warpages, stresses and keep-out zone in 3D through-silicon-via DRAM packages

M. Y. Tsai*, P. S. Huang, C. Y. Huang, P. C. Lin, Lawrence Huang, Michael Chang, Steven Shih, J. P. Lin

*Corresponding author for this work

Research output: Contribution to journalJournal Article peer-review

9 Scopus citations

Abstract

This paper aims to measure and simulate the warpages of 3D through-silicon via (TSV) die-stacked dynamic-random-access-memory (DRAM) packages during the manufacturing process. The related die stresses and keep-out zone (KOZ) for the stacked dies in the packages at room temperature are further calculated with the validated simulation model. The out-of-plane deformations (or warpages) of the packages from the full-field shadow moiré are documented under temperature loading and found consistent with those from finite-element method (FEM). The results of the stresses and KOZs at the proximity of a single TSV for each die in the package at room temperature are presented. It is found that the sizes of KOZs in four-die stacked DRAM packages with and without epoxy molding compound (EMC) at room temperature are dominated by the horizontal pMOS transistors and more than double the size in wafer-level die. The sizes of KOZs at each die are similar in this four-die stacked DRAM package, even though the stresses at each die are apparently different.

Original languageEnglish
Pages (from-to)2898-2904
Number of pages7
JournalMicroelectronics Reliability
Volume54
Issue number12
DOIs
StatePublished - 01 12 2014

Bibliographical note

Publisher Copyright:
© 2014 Elsevier Ltd. All right reserved.

Keywords

  • 3D IC package
  • Keep-out zone (KOZ)
  • Mobility change
  • Stress
  • Through silicon via (TSV)
  • Warpage

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