Analysis of various body bias under near-Threshold-voltage CMOS circuits

I. Chyn Wey; Jing Yi Huang

doi:10.1109/ICASI.2017.7988496

Analysis of various body bias under near-Threshold-voltage CMOS circuits

I. Chyn Wey
, Jing Yi Huang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In this paper, we analyzed near-Threshold-voltage (NTV) CMOS circuits with various body bias and proposed an NTV adder design with dual body bias. By adopting different body bias in the same time, adder delay and leakage power can be reduced. Also, the critical path is optimized to achieve better energy efficiency. The performance analysis are all performed under TSMC 90nm CMOS process with Monte Carlo simulation.

Original language	English
Title of host publication	Proceedings of the 2017 IEEE International Conference on Applied System Innovation
Subtitle of host publication	Applied System Innovation for Modern Technology, ICASI 2017
Editors	Teen-Hang Meen, Artde Donald Kin-Tak Lam, Stephen D. Prior
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	606-609
Number of pages	4
ISBN (Electronic)	9781509048977
DOIs	https://doi.org/10.1109/ICASI.2017.7988496
State	Published - 21 07 2017
Event	2017 IEEE International Conference on Applied System Innovation, ICASI 2017 - Sapporo, Japan Duration: 13 05 2017 → 17 05 2017

Publication series

Name	Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017

Conference

Conference	2017 IEEE International Conference on Applied System Innovation, ICASI 2017
Country/Territory	Japan
City	Sapporo
Period	13/05/17 → 17/05/17

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Body bias
CMOS
Near-Threshold-voltage

Access to Document

10.1109/ICASI.2017.7988496

Cite this

Wey, I. C., & Huang, J. Y. (2017). Analysis of various body bias under near-Threshold-voltage CMOS circuits. In T.-H. Meen, A. D. K.-T. Lam, & S. D. Prior (Eds.), Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017 (pp. 606-609). Article 7988496 (Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICASI.2017.7988496

Wey, I. Chyn ; Huang, Jing Yi. / Analysis of various body bias under near-Threshold-voltage CMOS circuits. Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017. editor / Teen-Hang Meen ; Artde Donald Kin-Tak Lam ; Stephen D. Prior. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 606-609 (Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017).

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title = "Analysis of various body bias under near-Threshold-voltage CMOS circuits",

abstract = "In this paper, we analyzed near-Threshold-voltage (NTV) CMOS circuits with various body bias and proposed an NTV adder design with dual body bias. By adopting different body bias in the same time, adder delay and leakage power can be reduced. Also, the critical path is optimized to achieve better energy efficiency. The performance analysis are all performed under TSMC 90nm CMOS process with Monte Carlo simulation.",

keywords = "Body bias, CMOS, Near-Threshold-voltage",

author = "Wey, \{I. Chyn\} and Huang, \{Jing Yi\}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 IEEE International Conference on Applied System Innovation, ICASI 2017 ; Conference date: 13-05-2017 Through 17-05-2017",

year = "2017",

month = jul,

day = "21",

doi = "10.1109/ICASI.2017.7988496",

language = "英语",

series = "Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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booktitle = "Proceedings of the 2017 IEEE International Conference on Applied System Innovation",

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Wey, IC & Huang, JY 2017, Analysis of various body bias under near-Threshold-voltage CMOS circuits. in T-H Meen, ADK-T Lam & SD Prior (eds), Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017., 7988496, Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017, Institute of Electrical and Electronics Engineers Inc., pp. 606-609, 2017 IEEE International Conference on Applied System Innovation, ICASI 2017, Sapporo, Japan, 13/05/17. https://doi.org/10.1109/ICASI.2017.7988496

Analysis of various body bias under near-Threshold-voltage CMOS circuits. / Wey, I. Chyn; Huang, Jing Yi.
Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017. ed. / Teen-Hang Meen; Artde Donald Kin-Tak Lam; Stephen D. Prior. Institute of Electrical and Electronics Engineers Inc., 2017. p. 606-609 7988496 (Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Huang, Jing Yi

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AB - In this paper, we analyzed near-Threshold-voltage (NTV) CMOS circuits with various body bias and proposed an NTV adder design with dual body bias. By adopting different body bias in the same time, adder delay and leakage power can be reduced. Also, the critical path is optimized to achieve better energy efficiency. The performance analysis are all performed under TSMC 90nm CMOS process with Monte Carlo simulation.

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KW - CMOS

KW - Near-Threshold-voltage

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Wey IC, Huang JY. Analysis of various body bias under near-Threshold-voltage CMOS circuits. In Meen TH, Lam ADKT, Prior SD, editors, Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 606-609. 7988496. (Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017). doi: 10.1109/ICASI.2017.7988496

Analysis of various body bias under near-Threshold-voltage CMOS circuits

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