Analytical delay model of CMOS inverter including channel-length modulation

H. C. Chow; W. S. Feng

doi:10.1049/el:19920256

Analytical delay model of CMOS inverter including channel-length modulation

H. C. Chow, W. S. Feng

National Taiwan University

Research output: Contribution to journal › Journal Article › peer-review

2 Scopus citations

Abstract

An analytical delay model of a CMOS inverter is introduced for the first time which includes channel-length modulation, source-drain resistance and high-field effects. Calculations of the rise, fall and delay times show good agreement with SPICE simulations.

Original language	English
Pages (from-to)	408-410
Number of pages	3
Journal	Electronics Letters
Volume	28
Issue number	4
DOIs	https://doi.org/10.1049/el:19920256
State	Published - 02 1992
Externally published	Yes

Keywords

Fieldeffect transistors
Semiconductor devices and materials

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10.1049/el:19920256

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@article{ab18d73f030a44b3858bfea4fc089ef4,

title = "Analytical delay model of CMOS inverter including channel-length modulation",

abstract = "An analytical delay model of a CMOS inverter is introduced for the first time which includes channel-length modulation, source-drain resistance and high-field effects. Calculations of the rise, fall and delay times show good agreement with SPICE simulations.",

keywords = "Fieldeffect transistors, Semiconductor devices and materials",

author = "Chow, {H. C.} and Feng, {W. S.}",

year = "1992",

month = feb,

doi = "10.1049/el:19920256",

language = "英语",

volume = "28",

pages = "408--410",

journal = "Electronics Letters",

issn = "0013-5194",

publisher = "John Wiley & Sons Inc.",

number = "4",

}

TY - JOUR

T1 - Analytical delay model of CMOS inverter including channel-length modulation

AU - Chow, H. C.

AU - Feng, W. S.

PY - 1992/2

Y1 - 1992/2

N2 - An analytical delay model of a CMOS inverter is introduced for the first time which includes channel-length modulation, source-drain resistance and high-field effects. Calculations of the rise, fall and delay times show good agreement with SPICE simulations.

AB - An analytical delay model of a CMOS inverter is introduced for the first time which includes channel-length modulation, source-drain resistance and high-field effects. Calculations of the rise, fall and delay times show good agreement with SPICE simulations.

KW - Fieldeffect transistors

KW - Semiconductor devices and materials

UR - http://www.scopus.com/inward/record.url?scp=0026819497&partnerID=8YFLogxK

U2 - 10.1049/el:19920256

DO - 10.1049/el:19920256

M3 - 文章

AN - SCOPUS:0026819497

SN - 0013-5194

VL - 28

SP - 408

EP - 410

JO - Electronics Letters

JF - Electronics Letters

IS - 4

ER -

Analytical delay model of CMOS inverter including channel-length modulation

Abstract

Keywords

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