Area-efficient video transform for HEVC applications

Yuan Ho Chen; Chieh Yang Liu

doi:10.1049/el.2015.1085

Area-efficient video transform for HEVC applications

Yuan Ho Chen^*, Chieh Yang Liu

^*Corresponding author for this work

Department of Electronic Engineering

Chung Yuan Christian University

Research output: Contribution to journal › Journal Article › peer-review

6 Scopus citations

Abstract

A hardware design capable of supporting high-efficiency video coding (HEVC) inverse transform (IDCT) is developed for a 32-point transform unit using a single one-dimensional (1D) transform core with two transposed memories to reduce area overhead. The proposed 1D core employs two calculation paths to obtain high throughput and is able to calculate first-dimensional (1st-D) and second-dimensional (2nd-D) transformations simultaneously along two parallel paths. The results from a practical implementation of the chip demonstrate that the proposed design presents the smallest circuit area among existing 2D transform cores.

Original language	English
Pages (from-to)	1065-1067
Number of pages	3
Journal	Electronics Letters
Volume	51
Issue number	14
DOIs	https://doi.org/10.1049/el.2015.1085
State	Published - 09 07 2015

Bibliographical note

Publisher Copyright:
© The Institution of Engineering and Technology 2015.

Access to Document

10.1049/el.2015.1085

Cite this

@article{d9a7d0cd27c348d8b96e775e6f849a9a,

title = "Area-efficient video transform for HEVC applications",

abstract = "A hardware design capable of supporting high-efficiency video coding (HEVC) inverse transform (IDCT) is developed for a 32-point transform unit using a single one-dimensional (1D) transform core with two transposed memories to reduce area overhead. The proposed 1D core employs two calculation paths to obtain high throughput and is able to calculate first-dimensional (1st-D) and second-dimensional (2nd-D) transformations simultaneously along two parallel paths. The results from a practical implementation of the chip demonstrate that the proposed design presents the smallest circuit area among existing 2D transform cores.",

author = "Chen, {Yuan Ho} and Liu, {Chieh Yang}",

note = "Publisher Copyright: {\textcopyright} The Institution of Engineering and Technology 2015.",

year = "2015",

month = jul,

day = "9",

doi = "10.1049/el.2015.1085",

language = "英语",

volume = "51",

pages = "1065--1067",

journal = "Electronics Letters",

issn = "0013-5194",

publisher = "John Wiley & Sons Inc.",

number = "14",

}

TY - JOUR

T1 - Area-efficient video transform for HEVC applications

AU - Chen, Yuan Ho

AU - Liu, Chieh Yang

PY - 2015/7/9

Y1 - 2015/7/9

N2 - A hardware design capable of supporting high-efficiency video coding (HEVC) inverse transform (IDCT) is developed for a 32-point transform unit using a single one-dimensional (1D) transform core with two transposed memories to reduce area overhead. The proposed 1D core employs two calculation paths to obtain high throughput and is able to calculate first-dimensional (1st-D) and second-dimensional (2nd-D) transformations simultaneously along two parallel paths. The results from a practical implementation of the chip demonstrate that the proposed design presents the smallest circuit area among existing 2D transform cores.

AB - A hardware design capable of supporting high-efficiency video coding (HEVC) inverse transform (IDCT) is developed for a 32-point transform unit using a single one-dimensional (1D) transform core with two transposed memories to reduce area overhead. The proposed 1D core employs two calculation paths to obtain high throughput and is able to calculate first-dimensional (1st-D) and second-dimensional (2nd-D) transformations simultaneously along two parallel paths. The results from a practical implementation of the chip demonstrate that the proposed design presents the smallest circuit area among existing 2D transform cores.

UR - http://www.scopus.com/inward/record.url?scp=84936877928&partnerID=8YFLogxK

U2 - 10.1049/el.2015.1085

DO - 10.1049/el.2015.1085

M3 - 文章

AN - SCOPUS:84936877928

SN - 0013-5194

VL - 51

SP - 1065

EP - 1067

JO - Electronics Letters

JF - Electronics Letters

IS - 14

ER -

Area-efficient video transform for HEVC applications

Abstract

Bibliographical note

Access to Document

Other files and links

Fingerprint

Cite this