@inproceedings{d9336b46e9734044862e4f7bc90cafd7,
title = "Automatic partitioner for behavior level distributed logic simulation",
abstract = "As the complexity of circuit design increases, verification through simulation has become a bottleneck of the IC design process. Distributed parallel simulation is one way to solving the problem. In order to distribute the simulation workload to multiple processors, the design must be carefully partitioned first. While most previous work focus on gate level partitioning, our work extends a previously implemented Verilog gate-level partitioner to support RTL and behavior level partitioning. Techniques to partition special constructs specific to these levels, such as global access, function calls and memory access, are described in this paper. The experimental results show that our techniques are capable of finding partitions which can accelerate simulation.",
keywords = "Behavior level partitioner, Distributed simulation, Parallel simulation, RTL level partitioner",
author = "Chang, \{Kai Hui\} and Kang, \{Jeh Yen\} and Wang, \{Han Wei\} and Tu, \{Wei Ting\} and Yeh, \{Yi Jong\} and Kuo, \{Sy Yen\}",
year = "2005",
doi = "10.1007/11562436\_38",
language = "英语",
isbn = "354029189X",
series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
publisher = "Springer Verlag",
pages = "525--528",
editor = "Farn Wang",
booktitle = "Formal Techniques for Networked and Distributed Systems - FORTE 2005 - 25th IFIP WG 6.1 International Conference, Proceedings",
address = "德国",
note = "25th IFIP WG 6.1 International Conference on Formal Techniques for Networked and Distributed Systems - FORTE 2005 ; Conference date: 02-10-2005 Through 05-10-2005",
}