Automatic partitioner for distributed parallel logic simulation

As the complexity of circuit design increases, verification through simulation has become the bottleneck of the IC design process. Distributed parallel simulation is one way to solving the problem. In order to distribute the simulation to multiple processors, the design must be partitioned first. This paper describes the goal and criteria for a distributed simulation partitioner and proposed an algorithm to achieve it. While most existing partitioners focus on gate-level, this partitioner is designed for all levels of abstraction, from behavior level to gate level.