Binary-tree timing simulation with consideration of internal charges

J. J.H. Wang*, M. Chang, W. S. Feng

*Corresponding author for this work

Research output: Contribution to journalJournal Article peer-review

5 Scopus citations

Abstract

An accurate and efficient block-level timing simulator is described. The high accuracy is attributed to a sophisticated delay model, which includes an accurate representation of the wave-form, a consistent and meaningful definition of delay, a consideration of waveform slope effects at both input and output of a gate, a consideration of the multiple charging/discharging paths in the circuit, and a consideration of the various fan-out effect and various cell-size effects. Efficient delay calculation is accomplished through a logic-level simulator instead of using a transistor-level simulator. To represent the waveform accurately, the switching delay and slope are defined and calculated with consideration of the internal charges. To consider the internal charges when computing the waveform, a merged PN tree is used to represent a CMOS gate. The characteristics of the PN tree are described and the methods used to evaluate the conducting paths proposed. The relationship between the RC time constant and the slope waveform is investigated. After the conducting paths are obtained, a recursive algorithm can be applied to compute the RC time constant in series-parallel RC networks, followed by switching delay and slope. The results are satisfactory when compared with Spice.

Original languageEnglish
Pages (from-to)211-219
Number of pages9
JournalIEE Proceedings E: Computers and Digital Techniques
Volume140
Issue number4
DOIs
StatePublished - 1993
Externally publishedYes

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