Bit-parallel systolic modular multipliers for a class of GF(2m)

C. Y. Lee*, E. H. Lu, J. Y. Lee

*Corresponding author for this work

Research output: Contribution to conferenceConference Paperpeer-review

3 Scopus citations


In this paper, an effective algorithm for computing multiplication over a class of GF(2m) based on irreducible all one polynomials (AOP) and equally spaced polynomials (ESP) is presented. The structures are the use of two special operations, called the cyclic shifting and the inner product, to construct the low-latency bit-parallel systolic multipliers. The circuits are simple and modular which is important for hardware implementation. The AOP-based multiplier is composed of (m+1)2 identical cells, each of which consisting of one 2-bit AND gate, one 2-bit XOR gate and three 1-bit latches. This multiplier has very low latency and propagation delay, which makes them very fast. Moreover, the AOP-based multiplier of small size can also be applied to construct ESP-based multiplier of large size, in which the elements are represented with the root of an irreducible equally spaced polynomial of degree nr. It is shown that if, for a certain degree, an irreducible ESP of a large degree can b e obtained from a corresponding irreducible AOP of a very small degree. Then from the complexity point view, the structure of ESP-based multiplier is beneficial to construct modular architecture.

Original languageEnglish
Number of pages8
StatePublished - 2001
Event15th IEEE Symposium on Computer Arithmetic - Vail, CO, United States
Duration: 11 06 200113 06 2001


Conference15th IEEE Symposium on Computer Arithmetic
Country/TerritoryUnited States
CityVail, CO


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