Boomerang: Physical-Aware Design Space Exploration Framework on RISC-V SonicBOOM Microarchitecture

As semiconductor manufacturing technology advances, microarchitecture designers could use the advanced process to create complex microarchitectures, making the design more performant, power-saving, and area efficient. To get better designs for various objectives, designers use hardware description language to deploy a highly parameterizable hardware design generator. However, the more flexible the parameterized design is, the more complex the parameters to choose over the possible parameter space. Traditionally, experienced hardware engineers have to hand-tune each design parameter to achieve better performance, power, and area efficiency. Moreover, the design space is usually too large to practically explore by running place-and-route (PnR) of each design since the electronic design automation (EDA) tool could take days to finish it. Thus, prior works on microarchitecture search only focus on logical results, which leads the search framework to ignore the quality gap between logical and physical design, resulting in inaccurate Pareto frontier prediction. To further address this issue, we use the physical synthesis technique to estimate the physical characteristics and save runtime while exploring the design space simultaneously. In this case, we developed a heuristic idea, Physical-aware Design Space Exploration Framework on RISC-V SonicBOOM Microarchitecture, that optimizes the netlist and physical layout quality. It results in a much more accurate prediction of the Pareto parameter set with a 40% and 28% search time reduction on the three-objective and four-objective problems, respectively, compared to the best baseline model. In addition, our method achieved a seven times smaller hypervolume difference than the best baseline model within the same number of observations.