Bus-oriented dft design for embedded cores

Chih Yi Lin; Hsing Chung Liang

Bus-oriented dft design for embedded cores

Chih Yi Lin^*, Hsing Chung Liang

^*Corresponding author for this work

Department of Electronic Engineering

Chang Gung University

Research output: Contribution to conference › Conference Paper › peer-review

8 Scopus citations

Abstract

This paper presents a testable design method for the embedded cores in an object SoC chip. Instead of modifying the digital cores for testability consideration, we target on revising the AMBA bus for test application and response observation. The test information is transformed from a core's I/Os to the chip's external pins. Experimental results on some embedded cores have shown that the proposed method costs small area and timing overhead.

Original language	English
Pages	561-563
Number of pages	3
State	Published - 2004
Event	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan Duration: 06 12 2004 → 09 12 2004

Conference

Conference	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
Country/Territory	Taiwan
City	Tainan
Period	06/12/04 → 09/12/04

Cite this

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abstract = "This paper presents a testable design method for the embedded cores in an object SoC chip. Instead of modifying the digital cores for testability consideration, we target on revising the AMBA bus for test application and response observation. The test information is transformed from a core's I/Os to the chip's external pins. Experimental results on some embedded cores have shown that the proposed method costs small area and timing overhead.",

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AB - This paper presents a testable design method for the embedded cores in an object SoC chip. Instead of modifying the digital cores for testability consideration, we target on revising the AMBA bus for test application and response observation. The test information is transformed from a core's I/Os to the chip's external pins. Experimental results on some embedded cores have shown that the proposed method costs small area and timing overhead.

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T2 - 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology

Y2 - 6 December 2004 through 9 December 2004

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Bus-oriented dft design for embedded cores

Abstract

Conference

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