Clique partitioning based integrated architecture synthesis for VLSI chips

Jer Min Jou; Shiann Rong Kuang; Ren Der Chen

doi:10.1109/VTSA.1993.263627

Clique partitioning based integrated architecture synthesis for VLSI chips

Jer Min Jou
, Shiann Rong Kuang
, Ren Der Chen

National Cheng Kung University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

The tasks as module selection, scheduling and allocation involved in the architecture synthesis problem of VLSI chips are tightly interdependent. Simultaneous optimization of these tasks is necessary for the global solution of a design. In this paper, we present a new graph model for the integrated architecture synthesis problem of VLSI chips and then formulate the problem as a partial clique partition problem and solve it globally using a heuristic. We have tested our approach using examples from the literature and experimental results show that our approach is better then or as good as other published approaches.

Original language	English
Title of host publication	1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	58-62
Number of pages	5
ISBN (Electronic)	0780309782
DOIs	https://doi.org/10.1109/VTSA.1993.263627
State	Published - 1993
Externally published	Yes
Event	1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Taipei, Taiwan Duration: 12 05 1993 → 14 05 1993

Publication series

Name	International Symposium on VLSI Technology, Systems, and Applications, Proceedings
ISSN (Print)	1930-8868

Conference

Conference	1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993
Country/Territory	Taiwan
City	Taipei
Period	12/05/93 → 14/05/93

Bibliographical note

Publisher Copyright:
© 1993 IEEE.

Access to Document

10.1109/VTSA.1993.263627

Cite this

Jou, J. M., Kuang, S. R., & Chen, R. D. (1993). Clique partitioning based integrated architecture synthesis for VLSI chips. In 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers (pp. 58-62). Article 263627 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VTSA.1993.263627

Jou, Jer Min ; Kuang, Shiann Rong ; Chen, Ren Der. / Clique partitioning based integrated architecture synthesis for VLSI chips. 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 1993. pp. 58-62 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings).

@inproceedings{71e1369c54204e7abab551a380d16ec3,

title = "Clique partitioning based integrated architecture synthesis for VLSI chips",

abstract = "The tasks as module selection, scheduling and allocation involved in the architecture synthesis problem of VLSI chips are tightly interdependent. Simultaneous optimization of these tasks is necessary for the global solution of a design. In this paper, we present a new graph model for the integrated architecture synthesis problem of VLSI chips and then formulate the problem as a partial clique partition problem and solve it globally using a heuristic. We have tested our approach using examples from the literature and experimental results show that our approach is better then or as good as other published approaches.",

author = "Jou, \{Jer Min\} and Kuang, \{Shiann Rong\} and Chen, \{Ren Der\}",

note = "Publisher Copyright: {\textcopyright} 1993 IEEE.; 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 ; Conference date: 12-05-1993 Through 14-05-1993",

year = "1993",

doi = "10.1109/VTSA.1993.263627",

language = "英语",

series = "International Symposium on VLSI Technology, Systems, and Applications, Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "58--62",

booktitle = "1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers",

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}

Jou, JM, Kuang, SR & Chen, RD 1993, Clique partitioning based integrated architecture synthesis for VLSI chips. in 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers., 263627, International Symposium on VLSI Technology, Systems, and Applications, Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 58-62, 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993, Taipei, Taiwan, 12/05/93. https://doi.org/10.1109/VTSA.1993.263627

Clique partitioning based integrated architecture synthesis for VLSI chips. / Jou, Jer Min; Kuang, Shiann Rong; Chen, Ren Der.
1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 1993. p. 58-62 263627 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Clique partitioning based integrated architecture synthesis for VLSI chips

AU - Jou, Jer Min

AU - Kuang, Shiann Rong

AU - Chen, Ren Der

PY - 1993

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N2 - The tasks as module selection, scheduling and allocation involved in the architecture synthesis problem of VLSI chips are tightly interdependent. Simultaneous optimization of these tasks is necessary for the global solution of a design. In this paper, we present a new graph model for the integrated architecture synthesis problem of VLSI chips and then formulate the problem as a partial clique partition problem and solve it globally using a heuristic. We have tested our approach using examples from the literature and experimental results show that our approach is better then or as good as other published approaches.

AB - The tasks as module selection, scheduling and allocation involved in the architecture synthesis problem of VLSI chips are tightly interdependent. Simultaneous optimization of these tasks is necessary for the global solution of a design. In this paper, we present a new graph model for the integrated architecture synthesis problem of VLSI chips and then formulate the problem as a partial clique partition problem and solve it globally using a heuristic. We have tested our approach using examples from the literature and experimental results show that our approach is better then or as good as other published approaches.

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DO - 10.1109/VTSA.1993.263627

M3 - 会议稿件

AN - SCOPUS:84949751015

T3 - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

SP - 58

EP - 62

BT - 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993

Y2 - 12 May 1993 through 14 May 1993

ER -

Jou JM, Kuang SR, Chen RD. Clique partitioning based integrated architecture synthesis for VLSI chips. In 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 1993. p. 58-62. 263627. (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). doi: 10.1109/VTSA.1993.263627

Clique partitioning based integrated architecture synthesis for VLSI chips

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