Clock-aware placement for large-scale heterogeneous FPGAs

Yun Chih Kuo; Chau Chin Huang; Shih Chun Chen; Chun Han Chiang; Yao Wen Chang; Sy Yen Kuo

doi:10.1109/ICCAD.2017.8203821

Clock-aware placement for large-scale heterogeneous FPGAs

Yun Chih Kuo
, Chau Chin Huang
, Shih Chun Chen
, Chun Han Chiang
, Yao Wen Chang
, Sy Yen Kuo

National Taiwan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

17 Scopus citations

Abstract

A modern FPGA often contains an ASIC-like clocking architecture which is crucial to achieve better skew and performance. Existing conventional FPGA placement algorithms seldom consider clocking resources, and thus may lead to clock routing failures. To address the special FPGA clocking architecture, this paper presents a novel clock-aware placement algorithm for large-scale heterogeneous FPGAs. Our algorithm consists of three major stages: (1) a nonlinear global placement framework with clock fence region construction, (2) a clock-aware packing scheme, and (3) clock-aware legalization and detailed placement. We evaluate our results based on the 2017 ISPD Clock-Aware Placement Contest benchmark suite. Compared with the top three winners, the results show that our algorithm achieves the best overall routed wirelength. On average, our algorithm outperforms the top-3 winners by 3.6%, 7.5%, and 12.9% in routed wirelength, respectively.

Original language	English
Title of host publication	2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	519-526
Number of pages	8
ISBN (Electronic)	9781538630938
DOIs	https://doi.org/10.1109/ICCAD.2017.8203821
State	Published - 13 12 2017
Externally published	Yes
Event	36th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017 - Irvine, United States Duration: 13 11 2017 → 16 11 2017

Publication series

Name	IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Volume	2017-November
ISSN (Print)	1092-3152

Conference

Conference	36th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017
Country/Territory	United States
City	Irvine
Period	13/11/17 → 16/11/17

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

Access to Document

10.1109/ICCAD.2017.8203821

Cite this

Kuo, Y. C., Huang, C. C., Chen, S. C., Chiang, C. H., Chang, Y. W., & Kuo, S. Y. (2017). Clock-aware placement for large-scale heterogeneous FPGAs. In 2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017 (pp. 519-526). (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; Vol. 2017-November). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCAD.2017.8203821

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title = "Clock-aware placement for large-scale heterogeneous FPGAs",

abstract = "A modern FPGA often contains an ASIC-like clocking architecture which is crucial to achieve better skew and performance. Existing conventional FPGA placement algorithms seldom consider clocking resources, and thus may lead to clock routing failures. To address the special FPGA clocking architecture, this paper presents a novel clock-aware placement algorithm for large-scale heterogeneous FPGAs. Our algorithm consists of three major stages: (1) a nonlinear global placement framework with clock fence region construction, (2) a clock-aware packing scheme, and (3) clock-aware legalization and detailed placement. We evaluate our results based on the 2017 ISPD Clock-Aware Placement Contest benchmark suite. Compared with the top three winners, the results show that our algorithm achieves the best overall routed wirelength. On average, our algorithm outperforms the top-3 winners by 3.6\%, 7.5\%, and 12.9\% in routed wirelength, respectively.",

author = "Kuo, \{Yun Chih\} and Huang, \{Chau Chin\} and Chen, \{Shih Chun\} and Chiang, \{Chun Han\} and Chang, \{Yao Wen\} and Kuo, \{Sy Yen\}",

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doi = "10.1109/ICCAD.2017.8203821",

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Kuo, YC, Huang, CC, Chen, SC, Chiang, CH, Chang, YW & Kuo, SY 2017, Clock-aware placement for large-scale heterogeneous FPGAs. in 2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, vol. 2017-November, Institute of Electrical and Electronics Engineers Inc., pp. 519-526, 36th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017, Irvine, United States, 13/11/17. https://doi.org/10.1109/ICCAD.2017.8203821

Clock-aware placement for large-scale heterogeneous FPGAs. / Kuo, Yun Chih; Huang, Chau Chin; Chen, Shih Chun et al.
2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 519-526 (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; Vol. 2017-November).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Kuo, Yun Chih

AU - Huang, Chau Chin

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AU - Kuo, Sy Yen

PY - 2017/12/13

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N2 - A modern FPGA often contains an ASIC-like clocking architecture which is crucial to achieve better skew and performance. Existing conventional FPGA placement algorithms seldom consider clocking resources, and thus may lead to clock routing failures. To address the special FPGA clocking architecture, this paper presents a novel clock-aware placement algorithm for large-scale heterogeneous FPGAs. Our algorithm consists of three major stages: (1) a nonlinear global placement framework with clock fence region construction, (2) a clock-aware packing scheme, and (3) clock-aware legalization and detailed placement. We evaluate our results based on the 2017 ISPD Clock-Aware Placement Contest benchmark suite. Compared with the top three winners, the results show that our algorithm achieves the best overall routed wirelength. On average, our algorithm outperforms the top-3 winners by 3.6%, 7.5%, and 12.9% in routed wirelength, respectively.

AB - A modern FPGA often contains an ASIC-like clocking architecture which is crucial to achieve better skew and performance. Existing conventional FPGA placement algorithms seldom consider clocking resources, and thus may lead to clock routing failures. To address the special FPGA clocking architecture, this paper presents a novel clock-aware placement algorithm for large-scale heterogeneous FPGAs. Our algorithm consists of three major stages: (1) a nonlinear global placement framework with clock fence region construction, (2) a clock-aware packing scheme, and (3) clock-aware legalization and detailed placement. We evaluate our results based on the 2017 ISPD Clock-Aware Placement Contest benchmark suite. Compared with the top three winners, the results show that our algorithm achieves the best overall routed wirelength. On average, our algorithm outperforms the top-3 winners by 3.6%, 7.5%, and 12.9% in routed wirelength, respectively.

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Kuo YC, Huang CC, Chen SC, Chiang CH, Chang YW, Kuo SY. Clock-aware placement for large-scale heterogeneous FPGAs. In 2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 519-526. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD). doi: 10.1109/ICCAD.2017.8203821

Clock-aware placement for large-scale heterogeneous FPGAs

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