@inproceedings{050befb52b464e4289d7d0b4f3739898,
title = "Clock buffer with duty cycle corrector",
abstract = "A clock buffer with duty cycle corrector circuit is presented. The proposed circuit can generate either 50\% duty cycle or maintain duty cycle of input clock. It corrects the input duty cycle of 10\% 90\% for generated 50\% duty cycle of output clock. Moreover, it enhances the input clock signal driving ability and keeps duty cycle the same as duty cycle of input clock with range from 20\% 80\%. The proposed circuit operation frequency range is from 100MHz 1GHz. The proposed circuit has been fabricated in a 0.18um CMOS technology.",
author = "Kao, \{Shao Ku\} and You, \{Yong De\}",
year = "2010",
doi = "10.1109/SOCC.2010.5784648",
language = "英语",
isbn = "9781424466832",
series = "Proceedings - IEEE International SOC Conference, SOCC 2010",
pages = "293--296",
booktitle = "Proceedings - IEEE International SOC Conference, SOCC 2010",
note = "23rd IEEE International SOC Conference, SOCC 2010 ; Conference date: 27-09-2010 Through 29-09-2010",
}