CMOS amplifier design with enhanced slew rate and power supply rejection

Bang W. Lee; Bing J. Sheu

CMOS amplifier design with enhanced slew rate and power supply rejection

Bang W. Lee^*
, Bing J. Sheu

^*Corresponding author for this work

University of Southern California

Research output: Contribution to conference › Conference Paper › peer-review

Abstract

The performance of several types of analog VLSI circuits is limited by the settling behavior and power supply rejection of CMOS amplifiers. Three novel techniques in MOS amplifier design, including nonsaturated input differential pair, improved cascode structure, and biasing circuitry, are described. A two-stage amplifier using these techniques has been fabricated in the MOSIS scalable 2-μm CMOS technology, and achieves 80-V/μs slew rate and 57-dB power-supply rejection ratio (PSRR) at 50 kHz with DC power dissipation of 1 mW.

Original language	English
Pages	435-438
Number of pages	4
State	Published - 1990
Externally published	Yes
Event	Proceedings of the 32nd Midwest Symposium on Circuits and Systems Part 2 (of 2) - Champaign, IL, USA Duration: 14 08 1989 → 16 08 1989

Conference

Conference	Proceedings of the 32nd Midwest Symposium on Circuits and Systems Part 2 (of 2)
City	Champaign, IL, USA
Period	14/08/89 → 16/08/89

Cite this

@conference{c9d75c8ac920443a97e06e925ad68ff3,

title = "CMOS amplifier design with enhanced slew rate and power supply rejection",

abstract = "The performance of several types of analog VLSI circuits is limited by the settling behavior and power supply rejection of CMOS amplifiers. Three novel techniques in MOS amplifier design, including nonsaturated input differential pair, improved cascode structure, and biasing circuitry, are described. A two-stage amplifier using these techniques has been fabricated in the MOSIS scalable 2-μm CMOS technology, and achieves 80-V/μs slew rate and 57-dB power-supply rejection ratio (PSRR) at 50 kHz with DC power dissipation of 1 mW.",

author = "Lee, \{Bang W.\} and Sheu, \{Bing J.\}",

year = "1990",

language = "英语",

pages = "435--438",

note = "Proceedings of the 32nd Midwest Symposium on Circuits and Systems Part 2 (of 2) ; Conference date: 14-08-1989 Through 16-08-1989",

}

TY - CONF

T1 - CMOS amplifier design with enhanced slew rate and power supply rejection

AU - Lee, Bang W.

AU - Sheu, Bing J.

PY - 1990

Y1 - 1990

N2 - The performance of several types of analog VLSI circuits is limited by the settling behavior and power supply rejection of CMOS amplifiers. Three novel techniques in MOS amplifier design, including nonsaturated input differential pair, improved cascode structure, and biasing circuitry, are described. A two-stage amplifier using these techniques has been fabricated in the MOSIS scalable 2-μm CMOS technology, and achieves 80-V/μs slew rate and 57-dB power-supply rejection ratio (PSRR) at 50 kHz with DC power dissipation of 1 mW.

AB - The performance of several types of analog VLSI circuits is limited by the settling behavior and power supply rejection of CMOS amplifiers. Three novel techniques in MOS amplifier design, including nonsaturated input differential pair, improved cascode structure, and biasing circuitry, are described. A two-stage amplifier using these techniques has been fabricated in the MOSIS scalable 2-μm CMOS technology, and achieves 80-V/μs slew rate and 57-dB power-supply rejection ratio (PSRR) at 50 kHz with DC power dissipation of 1 mW.

UR - https://www.scopus.com/pages/publications/0025669780

M3 - 论文

AN - SCOPUS:0025669780

SP - 435

EP - 438

T2 - Proceedings of the 32nd Midwest Symposium on Circuits and Systems Part 2 (of 2)

Y2 - 14 August 1989 through 16 August 1989

ER -

CMOS amplifier design with enhanced slew rate and power supply rejection

Abstract

Conference

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