Abstract
The algorithm and architecture of a compact neural network based partial response maximum likelihood (PRML) detector with zero-forcing preprocessing for hard-disk drive reading channels are discussed. The data preprocessing technique to improve the performance and simulation result are also presented.
| Original language | English |
|---|---|
| Pages (from-to) | 9-12 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 3 |
| State | Published - 1998 |
| Externally published | Yes |
| Event | Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA Duration: 31 05 1998 → 03 06 1998 |