Compact VLSI design for recursive neural networks with hardware annealing capability

In this paper, we present a compact CMOS VLSI design for recursive neural networks with the capability of hardware annealing. Locally-connected recursive neural networks are a class of analog nonlinear networks which can solve many important optimization, and signal processing problems and is suitable for VLSI implementation because of its low demand on inter-cell connections. Hardware annealing, which is a paralleled version of effective mean-field annealing in analog networks, is a highly-efficient method to find global optimal solutions of recursive neural networks. A two-neuron prototype chip to demonstrate the functionality of hardware annealing is designed, analyzed and implemented in 2.0 μm CMOS technology using mixed-signal design methodology through MOSIS. For circuit reliabilty and compactness, a unit current of 6 μA is used. The cell density is 505 cells/cm² and the cell time constant time is designed to be 0.3 us. Laboratory experimental results to show the behavior of the two neuron chip was produced with annealing control signals from a function generator.