TY - GEN
T1 - Comparison of two data hazard handling schemes for asynchronous pipelined processors
AU - Chang, Meng Chou
AU - Shiau, Da Sen
PY - 2010
Y1 - 2010
N2 - Since asynchronous logic adopts a distributed control scheme, the traditional methods for handling hazards in synchronous processors cannot be directly applied to asynchronous processors. Recently, the data hazard detection table (DHDT) scheme has been regarded as an effective method for handling data hazards in asynchronous processors. In this paper, two asynchronous data hazard handling schemes, the DHDT scheme and the proposed destination register chain (DRC) scheme, are compared in terms of performance and hardware complexity. In order to evaluate these two data hazard handling schemes, we have used the Balsa asynchronous synthesis system to implement two asynchronous pipelined processors, AsynRISC-DHDT and AsynRISC-DRC, which employ DHDT and DRC, respectively, to deal with data hazards. Experimental results show that AsynRISC-DRC can achieve a 13% reduction in hardware area cost and a performance gain of 22.1% compared with AsynRISC-DHDT.
AB - Since asynchronous logic adopts a distributed control scheme, the traditional methods for handling hazards in synchronous processors cannot be directly applied to asynchronous processors. Recently, the data hazard detection table (DHDT) scheme has been regarded as an effective method for handling data hazards in asynchronous processors. In this paper, two asynchronous data hazard handling schemes, the DHDT scheme and the proposed destination register chain (DRC) scheme, are compared in terms of performance and hardware complexity. In order to evaluate these two data hazard handling schemes, we have used the Balsa asynchronous synthesis system to implement two asynchronous pipelined processors, AsynRISC-DHDT and AsynRISC-DRC, which employ DHDT and DRC, respectively, to deal with data hazards. Experimental results show that AsynRISC-DRC can achieve a 13% reduction in hardware area cost and a performance gain of 22.1% compared with AsynRISC-DHDT.
KW - Asynchronous logic
KW - Data hazard
KW - Data hazard detection table
KW - Pipelined processor
UR - http://www.scopus.com/inward/record.url?scp=77958540544&partnerID=8YFLogxK
U2 - 10.1109/ICCSIT.2010.5563539
DO - 10.1109/ICCSIT.2010.5563539
M3 - 会议稿件
AN - SCOPUS:77958540544
SN - 9781424455386
T3 - Proceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010
SP - 36
EP - 40
BT - Proceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010
T2 - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010
Y2 - 9 July 2010 through 11 July 2010
ER -