Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems

Sung Chuan Fang; Kuo En Chang; Wu Shiung Feng; Sao Jie Chen

doi:10.1145/127601.127629

Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems

Sung Chuan Fang^*, Kuo En Chang, Wu Shiung Feng, Sao Jie Chen

^*Corresponding author for this work

Department of Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Scopus citations

Abstract

A segment-crossing graph model is introduced, and a heuristic algorithm is proposed on the basis of this graph model. The algorithm is divided into two steps: Global Minimization and Local Minimization. In addition, practical considerations such as restricted terminals and adjacent limitations are addressed. The algorithm is evaluated by some routing examples using five layers. The results show that 45% of vias minimized are obtained on an average.

Original language	English
Title of host publication	Proceedings - Design Automation Conference
Publisher	Publ by IEEE
Pages	60-65
Number of pages	6
ISBN (Print)	0818691492, 9780818691492
DOIs	https://doi.org/10.1145/127601.127629
State	Published - 1991
Event	Proceedings of the 28th ACM/IEEE Design Automation Conference - San Francisco, CA, USA Duration: 17 06 1991 → 21 06 1991

Publication series

Name	Proceedings - Design Automation Conference
ISSN (Print)	0146-7123

Conference

Conference	Proceedings of the 28th ACM/IEEE Design Automation Conference
City	San Francisco, CA, USA
Period	17/06/91 → 21/06/91

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10.1145/127601.127629

Cite this

@inproceedings{03c701518b3e49dcbf6e995f5242801d,

title = "Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems",

abstract = "A segment-crossing graph model is introduced, and a heuristic algorithm is proposed on the basis of this graph model. The algorithm is divided into two steps: Global Minimization and Local Minimization. In addition, practical considerations such as restricted terminals and adjacent limitations are addressed. The algorithm is evaluated by some routing examples using five layers. The results show that 45% of vias minimized are obtained on an average.",

author = "Fang, {Sung Chuan} and Chang, {Kuo En} and Feng, {Wu Shiung} and Chen, {Sao Jie}",

year = "1991",

doi = "10.1145/127601.127629",

language = "英语",

isbn = "0818691492",

series = "Proceedings - Design Automation Conference",

publisher = "Publ by IEEE",

pages = "60--65",

booktitle = "Proceedings - Design Automation Conference",

note = "Proceedings of the 28th ACM/IEEE Design Automation Conference ; Conference date: 17-06-1991 Through 21-06-1991",

}

Fang, SC, Chang, KE, Feng, WS & Chen, SJ 1991, Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems. in Proceedings - Design Automation Conference. Proceedings - Design Automation Conference, Publ by IEEE, pp. 60-65, Proceedings of the 28th ACM/IEEE Design Automation Conference, San Francisco, CA, USA, 17/06/91. https://doi.org/10.1145/127601.127629

Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems. / Fang, Sung Chuan; Chang, Kuo En; Feng, Wu Shiung et al.
Proceedings - Design Automation Conference. Publ by IEEE, 1991. p. 60-65 (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems

AU - Fang, Sung Chuan

AU - Chang, Kuo En

AU - Feng, Wu Shiung

AU - Chen, Sao Jie

PY - 1991

Y1 - 1991

N2 - A segment-crossing graph model is introduced, and a heuristic algorithm is proposed on the basis of this graph model. The algorithm is divided into two steps: Global Minimization and Local Minimization. In addition, practical considerations such as restricted terminals and adjacent limitations are addressed. The algorithm is evaluated by some routing examples using five layers. The results show that 45% of vias minimized are obtained on an average.

AB - A segment-crossing graph model is introduced, and a heuristic algorithm is proposed on the basis of this graph model. The algorithm is divided into two steps: Global Minimization and Local Minimization. In addition, practical considerations such as restricted terminals and adjacent limitations are addressed. The algorithm is evaluated by some routing examples using five layers. The results show that 45% of vias minimized are obtained on an average.

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U2 - 10.1145/127601.127629

DO - 10.1145/127601.127629

M3 - 会议稿件

AN - SCOPUS:0026175672

SN - 0818691492

SN - 9780818691492

T3 - Proceedings - Design Automation Conference

SP - 60

EP - 65

BT - Proceedings - Design Automation Conference

PB - Publ by IEEE

T2 - Proceedings of the 28th ACM/IEEE Design Automation Conference

Y2 - 17 June 1991 through 21 June 1991

ER -

Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems

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